Revision History
| Date | Document Version | IP Version | Description |
|---|---|---|---|
| July 2025 | 3.2 | 5.13 | Corrected on Interrupt Status Register in Control Status Registers
R/W access attribute table. (DOC-2609) Added more details on the
Video Timing Parameter Definition table in the Video Timing
Parameters topic. |
| June 2025 | 3.1 | 5.12 | Added upper bound for pixel clk frequency. (SIP-952) Add ports to
get line and frame number. (SIP-943) Update reset sequence
descriptions. (DOC-2561) Added table Pixel Sideband
Interface in Ports. Added Note, Video Timing Waveform
(Horizontal) - Example for Accurate Frame Mode,and Video Timing
Waveform (Vertical) - Example for Accurate Frame Mode in Video
Timing Parameters. Updated Customizing the MIPI CSI-2 RX Controller, Pixel Clock Calculation, and Reset
Sequence and Initialization. Corrected description of
static delay adjustment in example design. |
| May 2025 | 3.0 | 5.11 | Updated example design. (SIP-891) Example Design IO bank update
(HVIO 3.3V). (SIP-907) Update default parameter value.
(SIP-910) Updated Customizing the MIPI CSI-2 RX Controller. Updated observation after
downloading bitstream and Example Design Implementation table in
Example Design. Updated Video Interface
table. Added Sideband Interface Ports table.
(DOC-2382) Updated Reset Sequence and Initialization
topic. (DOC-2485) |
| March 2025 | 2.9 | 5.10 | Removed unsupported dynamic delay control feature. (SIP-841) RTL
fix for HSIO RX HS ENABLE timing. (SIP-842). |
| January 2025 | 2.8 | 5.9 | Updated Figure Video Timing Waveform (Horizontal), Video Timing
Waveform (Vertical). (SIP-823) Example design update to align with
MIPI Utility change (DOC-1783). (SIP-792) |
| December 2024 | 2.7 | 5.8 | Added debug ports for internal signal observation and monitoring in Ports and Customizing the MIPI CSI-2 RX Controller. (SIP-580) |
| November 2024 | 2.6 | 5.7 | Added Topaz in Features and Device Support. (DOC-2102) Added IP
Version in Revision History. (DOC-2185) Soft DPHY 1.5Gbps
performance improvement. (SIP-614)Fix byte2pixel conversion issue
when ENABLE_VCX = 1. (SIP-759) |
| September 2024 | 2.5 | – |
Added 8 lanes support in Features and Table 1. (SIP-677)
Updated pixel data[63:0] in Figure 1.
Removed data type RGB666 from Table 1. (DOC-2068)
|
| July 2024 | 2.4 | – | Fixed error in Table 3. (DOC-2004) |
| June 2024 | 2.3 | – | Update Pixel FIFO depth requirement in table MIPI CSI-2 RX Controller
Core Parameter. (SIP-570) Revised supported lane number. Removed 8
from Features and MIPI CSI-2 RX Controller Core Parameter. (SIP-578)
Added Reset Sequence and Initialization
sub-section. |
| March 2024 | 2.2 | – | Added important note in Testbench regarding using default parameters
options only. (DOC-1781) Added testbench file for Modelsim and Aldec
simulation model support. (DOC-1782) |
| October 2023 | 2.1 | – |
Updated MIPI video data format tables to include RGB information.
(DOC-1474)
|
| July 2023 | 2.0 | – | Added more description for Accurate and Generic image frame modes. (DOC-1343) |
| June 2023 | 1.9 | – |
Added Device Support and release notes sections. (DOC-1234)
Updated supported data rate. (DOC-1217)
Updated port descriptions.
Added RAW16, RAW20, RAW24, and RAW28 format support.
Updated MIPI Parallel Clock Frequency, IP Core Clock Frequency,
Pixel Data FIFO Depth Size, Pack Type40, Pack Type48, Pack Type56,
Pack Type64 parameters.
Improved Interrupt Enable Register Definition descriptions.
Editorial changes.
|
| April 2023 | 1.8 | – | Updated tHS_PREPARE_ZERO (ns) description to indicate that includes tHS_ZERO. (DOC-1186) |
| February 2023 | 1.7 | – | Added note about the resource and performance values in the resource and utilization table are for guidance only. |
| August 2022 | 1.6 | – | Updated Control Status Register note. (DOC-898) |
| August 2022 | 1.5 | – |
Added video parameters waveform, and port clock domains.
(DOC-819)
|
| January 2022 | 1.4 | – | Improved description about CSR is accessed through AXI4-Lite
interface. (DOC-690) Corrected interrupt status register width and
improved D-PHY stop state status description.
(DOC-697) Updated resource utilization table.
(DOC-700) |
| December 2021 | 1.3 | – | Added simulation testbench. Added new IP manager
parameters. Added new ports. |
| November 2021 | 1.2 | – | Added support for 8 data lanes. (DOC-604) |
| October 2021 | 1.1 | – | Added note to state that the fMAX in Resource Utilization
and Performance, and Example Design Implementation tables were based on
default parameter settings. Updated design example target board to
production Titanium Ti60 F225 Development Board and updated
Resource Utilization and Performance, and Example Design
Implementation tables. (DOC-553) |
| June 2021 | 1.0 | – | Initial release. |