Video Timing Parameters
The following waveforms show the video interface signals relationship.
Note: In Generic mode, there are no incoming
byte packets for Line Start and Line End. Thus, a decoded hsync output is unable to
carry any information about the origin HFP and HBP of a horizontal line. Instead, the
hsync output follows the valid signal assertion and deassertion of a valid pixel data
type (except for embedded 8-bit data type, which is non-image data; therefore, the hsync
is not asserted according to the pixel data valid).
Note: Since there is no precise pixel interface timing information
from the received packets (byte clk domain), the pixel interface signal may not be
accurately represented by the waveform, e.g., the falling edge of hsync may be coming
earlier or later than pixel data valid (shaded area), depending on the byte clk, pixel
clk, and data type for byte2pixel conversion. If the falling edge of hsync is critical,
you need to extend the original HFP period in TX.
| MIPI Video Timing Parameters | Definition | Min | Max | Unit |
|---|---|---|---|---|
| HACT | Total number of pixel per line | 16 | 8,192 | Pixel |
| VACT | Total number of line per frame | 1 | 8,192 | Line |
| HSA | HSYNC pulse width | 1 | 4,096 | Pixel |
| HBP | Horizontal back porch | 1 | 4,096 | Pixel |
| HFP | Horizontal front porch | 1 | 4,096 | Pixel |
| VSA | VSYNC pulse width | 1 | 8,192 | Line |
| VBP | Vertical back porch | 1 | 8,192 | Line |
| VFP | Vertical front porch | 1 | 8,192 | Line |
| Pixel Clock | Video stream pixel clock frequency in MHz | 1 | 1 | MHz |
| MIPI Speed | CSI-2 RX MIPI speed in Mbps | 80 | 1,500 | Mbps |
| No. data lane | Number of MIPI data lane | 1 | 8 | Lane |
Table 1 describes the support range for video timing parameters. For a more precise check on timing compliance, you can refer to the Titanium MIPI Utility.
1 Refer to Pixel Clock Calculation.