Efinix, Inc.
  • Introduction
  • Features
  • Device Support
  • Resource Utilization and Performance
  • Release Notes
  • Functional Description
    • Ports
    • Pixel Clock Calculation
    • Control Status Registers
    • Pixel Encoding
    • MIPI RX Video Data DATA[63:0] Formats
    • Video Timing Parameters
    • Reset Sequence and Initialization
  • IP Manager
  • Customizing the MIPI CSI-2 RX Controller
  • MIPI CSI-2 RX Controller Example Design
  • MIPI CSI-2 RX Controller Testbench
  • Revision History

Functional Description

The MIPI CSI-2 RX Controller consists of a RX D-PHY block, lane aligner, control status registers, ECC and CRC checkers, depacketizer, and byte-to pixel converter. The core has a camera, AXI4-lite, MIPI RX I/O, and clock and reset interfaces.

Figure 1. MIPI CSI-2 RX Controller System Block Diagram
  • Ports
  • Pixel Clock Calculation
  • Control Status Registers
  • Pixel Encoding
  • MIPI RX Video Data DATA[63:0] Formats
  • Video Timing Parameters
  • Reset Sequence and Initialization

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