Customizing the MIPI CSI-2 RX Controller
The core has parameters so you can customize its function. You set the parameters in the General tab of the core's IP Configuration window.
| Name | Option | Description |
|---|---|---|
| Data Lanes | 1, 2, 4, 8 | Number of data lanes. Default: 4 |
| MIPI Parallel Clock Frequency | 10 – 187 | MIPI parallel clock (clk_byte_HS) frequency in MHz to support
data rate of 80 Mbps to 1500 Mbps. Default: 187 |
| IP Core Clock Frequency | 40 - 100 | IP core clock frequency in MHz Default: 100 |
| D-PHY Clock Mode | Continuous, Discontinuous | To enable discontinuous or continuous HS mode clock. Default:
Continuous |
| Pixel Data FIFO Depth | 256 - 8192 | FIFO depth size that stores the pixel packet data (set to power
of 2 value). Minimum FIFO depth required > horizontal_pixel
(HACT) x bits_per_pixel / 64 Default:
1024 |
| Image Frame Mode | GENERIC, ACCURATE | Select the image frame mode: Generic mode: Frame format
without accurate synchronization timing via Line Start and Line
End. Accurate mode: Frame format with accurate
synchronization timing via Line Start and Line
End. Default: Generic |
| Enable Pipeline State for RXStopState Signal | 8 – 15 | To enable pipeline stage for RXStopState signal. The pipeline
registers are clocked with HS mode byte clock. Compensates the
MIPI HSIO deserializer, read FIFO and data synchronizer latency
in designs with low MIPI data rate. Default:
8 |
| tLPX (ns) | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. Default: 50 |
| tINIT (ns) | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. Default:
100000 |
| tCLK_TERM_EN (ns) | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. Default: 38 |
| tD_TERM_EN (ns) | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns (value before adding
UI). Default: 35 |
| tHS_SETTLE (ns) | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns (value before adding
UI). Default: 85 |
| tHS_PREPARE_ZERO (ns) | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns (value before adding UI). This
parameter includes the tHS_ZERO parameter. Default:
145 |
| Pack Type 40 | Enable, Disable | Enables the controller to pack RAW10, RAW20, YUV_420_10, and
YUV_422_10 data type.1 Default: Enable |
| Pack Type 48 | Enable, Disable | Enables the controller to pack RAW6, RAW12, RAW24, RGB888, and
YUV_420_8_legacy data type.1 Default: Enable |
| Pack Type 56 | Enable, Disable | Enables the controller to pack RAW7, RAW14, and RAW28.1 Default: Enable |
| Pack Type 64 | Enable, Disable | Enables the controller to pack RAW8, RAW16, RGB444, RGB565,
RGB555, YUV_422_8, YUV_420_8, generic long packet, user define
8-bit, and embedded 8-bit non image packet.1 Default: Enable |
| Enable Extra Bits on Virtual Channel | Enable, Disable | Enables 16 virtual channel support. Default:
Disable |
| MIPI_CSI2_RX_DEBUG | Enable, Disable | Enables debug ports for internal signal observation and
monitoring. Default: Disable |
| MIPI_CSI2_RX_PIXEL_ SIDEBAND |
Enable, Disable | Enabels more sideband ports under pixel interface. Refer to
portlist for more details. Default: Disable |
1 Only enable the pack
type that you are using to save logic resources.