Ports

Table 1. Clock and Reset Ports

Port	Direction	Description
clk	Input	IP core clock consumed by controller logics. 100 MHz.
reset_n	Input	IP core reset signal.
clk_byte_HS	Input	MIPI RX parallel clock. This is a HS transmission clock.
reset_byte_HS_n	Input	MIPI RX parallel clock reset signal.
clk_pixel	Input	Pixel clock.
reset_pixel_n	Input	Pixel clock reset signal.
axi_clk	Input	AXI4-Lite interface clock.
axi_reset_n	Input	AXI4-Lite interface active low reset.

Table 2. MIPI RX I/O Interface

Port	Direction	Description
Rx_LP_CLK_P	Input	LP mode RX clock single-ended P signal.
Rx_LP_CLK_N	Input	LP mode RX clock single-ended N signal.
Rx_HS_enable_C	Output	Signal to enable HS mode clock lane.
LVDS_termen_C	Output	Signal to enable HS mode clock lane termination.
Rx_LP_D_P [NUM_DATA_LANE-1:0]	Input	LP mode RX data single-ended P signal.
Rx_LP_D_N [NUM_DATA_LANE-1:0]	Input	LP mode RX data single-ended N signal.
Rx_HS_D_n [7:0]	Input	HS mode differential lane data bus. n = lane 0 to 7
Rx_HS_enable_D [NUM_DATA_LANE-1:0]	Output	Signal to enable HS mode data lane.
LVDS_termen_D [NUM_DATA_LANE-1:0]	Output	Signal to enable HS mode data lane termination.
fifo_rd_enable [NUM_DATA_LANE-1:0]	Output	Rx HS mode data lane FIFO read enable signal.
fifo_rd_empty [NUM_DATA_LANE-1:0]	Input	Rx HS mode data lane FIFO empty signal.
DLY_enable_D [NUM_DATA_LANE-1:0]	Output	Reserved port.
DLY_inc_D [NUM_DATA_LANE-1:0]	Output	Reserved port.
u_dly_enable_D [NUM_DATA_LANE-1:0]	Input	Reserved port, Tie the signal to zero.
u_dly_inc_D [NUM_DATA_LANE-1:0]	Input	Reserved port. Tie the signal to zero.

Table 3. AXI4-Lite Interface

Interface to access Table 1.

All signals are clocked with axi_clk and axi_reset_n.

Port	Direction	Description
axi_awaddr [15:0]	Input	AXI4-Lite write address bus.
axi_awvalid	Input	AXI4-Lite write address valid strobe.
axi_awready	Output	AXI4-Lite write address ready signal.
axi_wdata [31:0]	Input	AXI4-Lite write data.
axi_wvalid	Input	AXI4-Lite write data valid strobe.
axi_wready	Output	AXI4-Lite write ready signal.
axi_bvalid	Output	AXI4-Lite write response valid strobe.
axi_bready	Input	AXI4-Lite write response ready signal.
axi_araddr [15:0]	Input	AXI4-Lite read address bus.
axi_arvalid	Input	AXI4-Lite read address valid strobe.
axi_arready	Output	AXI4-Lite read address ready signal.
axi_rdata [31:0]	Output	AXI4-Lite read data.
axi_rvalid	Output	AXI4-Lite read data valid strobe.
axi_rready	Input	AXI4-Lite read data ready signal.

Table 4. Video InterfaceAll signals are clocked with clk_pixel and reset_pixel_n. The hsync_vc and vsync_vc are level signals and not pulse signals. See Video Timing Parameters.

Port	Direction	Description
hsync_vcx	Output	Active-high horizontal sync for virtual channel. x = virtual lane 0 to 15
vsync_vcx	Output	Active-high vertical sync for virtual channel. x = virtual lane 0 to 15
pixel_data [63:0]	Output	Video Data. The actual data width of this port is dependent on pixel type. Refer to the pixel encoding table.
pixel_data_valid	Output	Active-high pixel data enable.
pixel_per_clk [15:0]	Output	Number of pixel per pixel clock. This signal only valid when pixel_data_valid flag is high.

Table 5. Sideband InterfaceAll signals are clocked by clk_byte_HS except irq which is clocked by axi_clk.

Port	Direction	Description
vc [1:0]	Output	2-bit virtual channel signal decoded from the packet header [7:6].
vcx [1:0]	Output	2-bit virtual channel signal decoded from the packet header [25:24].
word_count [15:0]	Output	Byte count of the long packet received by CSI2 RX controller.
datatype [5:0]	Output	Decoded data type of incoming packet received by CSI2 RX controller.
shortpkt_data_field [15:0]	Output	16-bit short packet data field for short packet.
irq	Output	Interrupt signal for Interrupt Status Register.

Table 6. Debug InterfaceAll signals are clocked with axi_clk and axi_reset_n.

Port	Direction	Description
mipi_debug_out[31:0]	Output	Debug port. Present if the parameter MIPI_CSI2_RX_DEBUG is Enabled. The following is the list of internal signals that can be monitored. [0] = pixel_fifo_full [1] = pixel_fifo_empty [2] = crc_error [3] = ecc_1bit_error [4] = ecc_2bit_error [5] = undersize_pkt_error [6] = line_vc0_error [7] = line_vc1_error [8] = line_vc2_error [9] = line_vc3_error [10] = frame_vc0_error [11] = frame_vc1_error [12] = frame_vc2_error [13] = frame_vc3_error [14] = receive_error [15] = init_done [16] = RxErrSotSyncHS_0 [17] = RxErrControl_0 [18] = RxErrEsc_0 [19] = RxStopState_0 [20] = RxSkewCalHS_0 [21] = RxUlpsActiveNot_0 [22] = RxUlpsEsc_0 [31:23] = reserved
mipi_debug_in[31:0]	Input	Debug ports. Present if the parameter MIPI_CSI2_RX_DEBUG is Enabled. Currently no function has been implemented. Tie all input bits to zero. [31:0] = reserved

Table 7. Pixel Sideband InterfaceAll signals are clocked by clk_pixel and reset_pixel_n. These output ports are present when MIPI_CSI2_RX_PIXEL_SIDEBAND switch is set to ENABLE.

Port	Direction	Description
pixel_line_num[15:0]	Output	Line number decoded from the incoming short packet. This signal is valid or changes only when the hsync signal asserts from low to high.
pixel_frame_num[15:0]	Output	Frame number decoded from the incoming short packet. This signal is valid or changes when the vsync signal asserts from low to high.
pixel_datatype[5:0]	Output	Decoded data type of incoming packet received by the RX controller. This signal is valid or changes when the pixel_data_valid signal asserts from low to high.
pixel_wordcount[15:0]	Output	Decoded wordcount of incoming long packet received by the RX controller. This signal is valid or changes when the pixel_data_valid signal asserts from low to high.
pixel_vc[1:0]	Output	2-bit virtual channel signal decoded from the packet header [7:6]. This signal is valid or changes when the vsync/hsync/pixel_data_valid signal asserts from low to high.
pixel_vcx[1:0]	Output	2-bit virtual channel signal decoded from the packet header [25:24]. This signal is valid or changes when the vsync/hsync/pixel_data_valid signal asserts from low to high.