Control Status Registers

Table 1. Control Status Registers
Word Address Offset Name R/W Width (bits)
0x00 Interrupt Status Register Bit[1:0] - R
Bit[14:2] - R/W1C1
 15
0x04 Interrupt Enable Register R/W 15
0x08 D-PHY status for lane 0 R 8
0x0C D-PHY status for lane 1 R 8
0x10 D-PHY status for lane 2 R 8
0x14 D-PHY status for lane 3 R 8
0x18 D-PHY status for lane 4 R 8
0x1C D-PHY status for lane 5 R 8
0x20 D-PHY status for lane 6 R 8
0x24 D-PHY status for lane 7 R 8
0x28 D-PHY status for clock lane R 2
Table 2. Interrupt Status Register Definition (0x00)
Bit Name Description
0 Pixel FIFO full Pixel FIFO in the byte-to-pixel converter module is full.
1 Pixel FIFO empty Pixel FIFO in the byte-to-pixel converter module is empty.
2 CRC error CRC error indicator.
3 Ecc 1 bit error ECC with 1 bit error indicator.
4 Ecc 2 bit error ECC with 2 bit error indicator.
5 Undersize packet error The incoming MIPI HS data byte is lesser than the wordcount value.
6 VC0 Line number synchronization error Line number synchronization error for virtual channel 0.
7 VC1 Line number synchronization error Line number synchronization error for virtual channel 1.
8 VC2 Line number synchronization error Line number synchronization error for virtual channel 2.
9 VC3 Line number synchronization error Line number synchronization error for virtual channel 3.
10 VC0 Frame number synchronization error Frame number synchronization error for virtual channel 0.
11 VC1 Frame number synchronization error Frame number synchronization error for virtual channel 1.
12 VC2 Frame number synchronization error Frame number synchronization error for virtual channel 2.
13 VC3 Frame number synchronization error Frame number synchronization error for virtual channel 3.
14 Initialization error MIPI HS data is received before tInit is completed.
Table 3. Interrupt Enable Register Definition (0x04)Each enabled interrupt status bit is aggregated to the irq output port as indicator. By default, all interrupt enable registers are set to 1'b0 (disabled).
Bit Name Description
0 Pixel FIFO full full interrupt enable Enable interrupt generation for Pixel FIFO full status bit.
1 Pixel FIFO empty full interrupt enable Enable interrupt generation for Pixel FIFO empty status bit.
2 CRC error full interrupt enable Enable interrupt generation for CRC error status bit.
3 ECC 1 bit error full interrupt enable Enable interrupt generation for ECC 1 bit error status bit.
4 ECC 2 bit error full interrupt enable Enable interrupt generation for ECC 2 bit error status bit.
5 Undersize packet error full interrupt enable Enable interrupt generation for Undersize packet error status bit.
6 VC0 Line number synchronization error full interrupt enable Enable interrupt generation for VC0 Line number synchronization error status bit.
7 VC1 Line number synchronization error full interrupt enable Enable interrupt generation for VC1 Line number synchronization error status bit.
8 VC2 Line number synchronization error full interrupt enable Enable interrupt generation for VC2 Line number synchronization error status bit.
9 VC3 Line number synchronization error full interrupt enable Enable interrupt generation for VC3 Line number synchronization error status bit.
10 VC0 Frame number synchronization error full interrupt enable Enable interrupt generation for VC0 Frame number synchronization error status bit.
11 VC1 Frame number synchronization error full interrupt enable Enable interrupt generation for VC1 Frame number synchronization error status bit.
12 VC2 Frame number synchronization error full interrupt enable Enable interrupt generation for VC2 Frame number synchronization error status bit.
13 VC3 Frame number synchronization error full interrupt enable Enable interrupt generation for VC3 Frame number synchronization error status bit.
14 Initialization error full interrupt enable Enable interrupt generation for Initialization error status bit.
Table 4. D-PHY Status for Data Lanes Register Definition (0x08 – 0x24)
Bit Name Description
0 RxErrSotSyncHS Start-of-Transmission (SoT) Synchronization Error.
The core asserts this signal high for one cycle of RxWordClkHS if the HS SoT leader sequence is corrupted in a way that proper synchronization cannot be expected.
1 RxErrControl Control Error.
The core asserts this signal high when an incorrect Line state sequence is detected in LP and ALP modes. Once asserted, this signal remains asserted until the next transaction starts, so that the protocol can properly process the error.
2 RxErrEsc Escape Entry Error.
The core asserts this signal high if an unrecognized escape entry command is received in LP mode. Once asserted, this signal remains asserted until the next transaction starts, so that the protocol can properly process the error.
3 RxStopState Lane is in stop state.
4 Reserved Reserved
5 RxUlpsActiveNot Ultra Low Power State (ULPS) (not) Active.
The core deasserts this signal low to indicate that the data lane is in ULP state.
6 RxUlpsEsc Escape ULPS (Receive) mode.
The core asserts this signal high to indicate that the lane module has entered the ULPS, due to the detection of a received ULPS command. The lane module remains in this mode with RxUlpsEsc asserted until a Stop state is detected on the lane interconnect.
7 Reserved Reserved
Table 5. D-PHY Status for Clock Lane Register Definition (0x28)
Bit Name Description
0 RxUlpsActiveClkNot ULPS (not) Active.
The core asserts this signal high to indicate that the clock lane is in ULPS.
1 RxUlpsClkNot Receive ULPS on Clock Lane.
The core deasserts this signal low to indicate that the clock lane module has entered the ULPS due to the detection of a request to enter the ULPS. The lane module remains in this mode with RxUlpsClkNot asserted until a stop state is detected on the lane interconnect.
1 Read register. Write 1 to clear the register.