Resource Utilization and Performance

Note: The resources and performance values provided are based on some of the supported FPGAs. These values are just guidance and may change depending on the device resource utilization, design congestion, and user design.

Table 2. Titanium Resource Utilization and Performance
FPGA	Mode	Logic and Adders	Flip-flops	Memory Blocks	DSP48 Blocks	f_MAX (MHz)^¹	Efinity® Version^²
Ti60 F225 C4	Master	217	175	0	0	561	2021.2
Ti60 F225 C4	Slave	216	175	0	0	438	2021.2

Table 3. Trion Resource Utilization and Performance
FPGA	Mode	Logic Utilization (LUTs)	Registers	Memory Blocks	Multipliers	f_MAX (MHz)^¹	Efinity® Version^²
T20 BGA256 C4	Master	441	203	0	0	154	2021.1
T20 BGA256 C4	Slave	258	198	0	0	210	2021.1

¹ Using default parameter settings.

² Using Verilog HDL.