Features

• Supports native user interface
• Master, slave, and multi-master operations
• Supports 100 kHz and 400 kHz I²C operation mode
• START, Repeated START and STOP signal generation and detection
• 7-bit slave addressing mode
• Verilog HDL RTL and simulation testbench
• Includes example designs targeting the Trion® T20 BGA256 Development Board and Titanium Ti60 F225 Development Board
• Supports SDA and SCL spike filtering, and SCL clock stretching