Ti180 PLL

Ti180 FPGAs have 8 PLLs to synthesize clock frequencies. The PLLs are located in the corners of the FPGA. You can use the PLL to compensate for clock skew/delay via external or internal feedback to meet timing requirements in advanced applications. The PLL reference clock has up to four sources. You can dynamically select the PLL reference clock with the CLKSEL port. (Hold the PLL in reset when dynamically selecting the reference clock source.)

The PLL consists of a pre-divider counter (N counter), a feedback multiplier counter (M counter), a post-divider counter (O counter), and output dividers (C).

At startup, Efinix recommends that you hold the PLL in reset until the PLL's reference clock source is stable.

Note: You can cascade PLLs. To avoid the PLL losing lock, Efinix recommends that you do not cascade more than two PLLs.

At startup, Efinix recommends resetting all cascaded PLLs. Hold the first PLL in reset until the PLL's reference clock source is stable. Hold the cascaded PLLs in reset until the previous PLL is locked.

Cascaded PLLs do not need a 50% duty cycle on the reference clock. However, the clock needs to meet the PLL minimum pulse width as specified in the data sheet.

The counter settings define the PLL output frequency:


Local and Core Feedback Mode	Where:
F_PFD = F_IN / N F_VCO = (F_PFD x M x O x C_FBK ) ¹ F_PLL = F_VCO / O F_OUT = (F_IN x M x C_FBK) / (N x C)	F_VCO is the voltage control oscillator frequency F_PLL is the post-divider PLL VCO frequency F_OUT is the output clock frequency F_IN is the reference clock frequency F_PFD is the phase frequency detector input frequency O is the post-divider counter C is the output divider

Note: Refer to the Ti180 PLL Timing and AC Characteristics for F_VCO, F_OUT, F_IN, F_PLL, and F_PFD values.

Table 1. PLL Signals (Interface to FPGA Fabric)
Signal	Direction	Description
CLKIN[3:0]	Input	Reference clocks driven by I/O pads or core clock tree.
CLKSEL[1:0]	Input	You can dynamically select the reference clock from one of the clock in pins.
RSTN	Input	Active-low PLL reset signal. When asserted, this signal resets the PLL; when de-asserted, it enables the PLL. De-assert only when the CLKIN signal is stable. Connect this signal in your design to power-up or reset the PLL. Assert the RSTN pin for a minimum pulse of 10 ns to reset the PLL. Assert RSTN when dynamically changing the selected PLL reference clock.
FBK	Input	Connect to a clock out interface pin when the PLL is in when the PLL is not in internal feedback mode.
CLKOUT0 CLKOUT1 CLKOUT2 CLKOUT3 CLKOUT4	Output	PLL output. You can route these signals as input clocks to the core's GCLK network. You can use CLKOUT0 only for clocks with a maximum frequency of 4x (integer) of the reference clock. If all your system clocks do not fall within this range, you should dedicate one unused clock for CLKOUT0.
LOCKED	Output	Goes high when PLL achieves lock; goes low when a loss of lock is detected. Connect this signal in your design to monitor the lock status. This signal is not synchronized to any clock and the minimum high or low pulse width of the lock signal may be smaller than the CLKOUT’s period.
SHIFT[2:0]	Input	(Optional) Dynamically change the phase shift of the output selected to the value set with this signal. Possible values from 000 (no phase shift) to 111 (3.5 F_PLL cycle delay). Each increment adds 0.5 cycle delay.
SHIFT_SEL[4:0]	Input	(Optional) Choose the output(s) affected by the dynamic phase shift.
SHIFT_ENA	Input	(Optional) When high, changes the phase shift of the selected PLL(s) to the new value.

Table 2. PLL Reference Clock Resource Assignments (J361)
PLL	REFCLK0	REFCLK1	External Feedback I/O
PLL_BL0	Single-ended: GPIOB_P_00_PLLIN0	Single-ended: GPIOL_00_PLLIN1	Single-ended: GPIOB_P_01_EXTFB Differential: GPIOB_P_01_EXTFB, GPIOB_N_01_CCK
PLL_BL1	Single-ended: GPIOB_P_11_PLLIN0 Differential: GPIOB_P_11_PLLIN0, GPIOB_N_11	Unbonded^²	Single-ended: GPIOB_P_12_EXTFB Differential: GPIOB_P_12_EXTFB, GPIOB_N_12_SSU_N
PLL_BL2	Single-ended: GPIOB_P_23_PLLIN0 Differential: GPIOB_P_23_PLLIN0, GPIOB_N_23_CDI12	Unbonded^²	Single-ended: GPIOB_P_24_EXTFB Differential: GPIOB_P_24_EXTFB, GPIOB_N_24_CDI13
PLL_TL0	Unbonded^²	Single-ended: GPIOL_26_PLLIN1	Unbonded^²
PLL_TL1	Single-ended: GPIOT_P_11_PLLIN0 Differential: GPIOT_P_11_PLLIN0, GPIOT_N_11	Single-ended: GPIOL_36_PLLIN1	Single-ended: GPIOT_P_12_EXTFB Differential: GPIOT_P_12_EXTFB, GPIOT_N_12
PLL_TL2	Single-ended: GPIOT_P_23_PLLIN0 Differential: GPIOT_P_23_PLLIN0, GPIOT_N_23	Single-ended: GPIOL_32_PLLIN1	Single-ended: GPIOT_P_24_EXTFB Differential: GPIOT_P_24_EXTFB, GPIOT_N_24
PLL_TR	Single-ended: GPIOR_P_45_PLLIN0 Differential: GPIOR_P_45_PLLIN0, GPIOR_N_45	Single-ended: GPIOR_P_31_PLLIN1 Differential: GPIOR_P_31_PLLIN1, GPIOR_N_31	Single-ended: GPIOR_P_44_EXTFB Differential: GPIOR_P_44_EXTFB, GPIOR_N_44
PLL_BR	Unbonded^²	Single-ended: GPIOR_P_16_PLLIN1 Differential: GPIOR_P_16_PLLIN1, GPIOR_N_16	Unbonded^²

Table 3. PLL Reference Clock Resource Assignments (L484, J484, M484)
PLL	REFCLK0	REFCLK1	External Feedback I/O
PLL_BL0	Single-ended: GPIOB_P_00_PLLIN0	Single-ended: GPIOL_00_PLLIN1	Single-ended: GPIOB_P_01_EXTFB Differential: GPIOB_P_01_EXTFB, GPIOB_N_01_CCK
PLL_BL1	Single-ended: GPIOB_P_11_PLLIN0 Differential: GPIOB_P_11_PLLIN0, GPIOB_N_11	Unbonded^²	Single-ended: GPIOB_P_12_EXTFB Differential: GPIOB_P_12_EXTFB, GPIOB_N_12_SSU_N
PLL_BL2	Single-ended: GPIOB_P_23_PLLIN0 Differential: GPIOB_P_23_PLLIN0, GPIOB_N_23_CDI12	Unbonded^²	Single-ended: GPIOB_P_24_EXTFB Differential: GPIOB_P_24_EXTFB, GPIOB_N_24_CDI13
PLL_TL0	Unbonded^²	Single-ended: GPIOL_26_PLLIN1	Unbonded^²
PLL_TL1	Single-ended: GPIOT_P_11_PLLIN0 Differential: GPIOT_P_11_PLLIN0, GPIOT_N_11	Single-ended: GPIOL_36_PLLIN1	Single-ended: GPIOT_P_12_EXTFB Differential: GPIOT_P_12_EXTFB, GPIOT_N_12
PLL_TL2	Unbonded^²	Single-ended: GPIOL_32_PLLIN1	Unbonded^²
PLL_TR	Single-ended: GPIOR_P_45_PLLIN0 Differential: GPIOR_P_45_PLLIN0, GPIOR_N_45	Single-ended: GPIOR_P_31_PLLIN1 Differential: GPIOR_P_31_PLLIN1, GPIOR_N_31	Single-ended: GPIOR_P_44_EXTFB Differential: GPIOR_P_44_EXTFB, GPIOR_N_44
PLL_BR	Unbonded^²	Single-ended: GPIOR_P_16_PLLIN1 Differential: GPIOR_P_16_PLLIN1, GPIOR_N_16	Unbonded^²

Table 4. PLL Reference Clock Resource Assignments (J484D1)
PLL	REFCLK0	REFCLK1	External Feedback I/O
PLL_BL0	Single-ended: GPIOB_P_00_PLLIN0	Single-ended: GPIOL_00_PLLIN1	Single-ended: GPIOB_P_01_EXTFB Differential: GPIOB_P_01_EXTFB, GPIOB_N_01_CCK
PLL_BL1	Single-ended: GPIOB_P_11_PLLIN0 Differential: GPIOB_P_11_PLLIN0, GPIOB_N_11	GPIOL_10_PLLIN1	Single-ended: GPIOB_P_12_EXTFB Differential: GPIOB_P_12_EXTFB, GPIOB_N_12_SSU_N
PLL_BL2	Single-ended: GPIOB_P_23_PLLIN0 Differential: GPIOB_P_23_PLLIN0, GPIOB_N_23_CDI12	GPIOL_20_PLLIN1	Single-ended: GPIOB_P_24_EXTFB Differential: GPIOB_P_24_EXTFB, GPIOB_N_24_CDI13
PLL_TL0	Unbonded^³	Single-ended: GPIOL_26_PLLIN1	Unbonded^³
PLL_TL1	Single-ended: GPIOT_P_11_PLLIN0 Differential: GPIOT_P_11_PLLIN0, GPIOT_N_11	Single-ended: GPIOL_36_PLLIN1	Single-ended: GPIOT_P_12_EXTFB Differential: GPIOT_P_12_EXTFB, GPIOT_N_12
PLL_TL2	Single-ended: GPIOT_P_23_PLLIN0 Differential: GPIOT_P_23_PLLIN0, GPIOT_N_23	Single-ended: GPIOL_32_PLLIN1	Single-ended: GPIOT_P_24_EXTFB Differential: GPIOT_P_24_EXTFB, GPIOT_N_24
PLL_TR	Single-ended: GPIOR_P_45_PLLIN0 Differential: GPIOR_P_45_PLLIN0, GPIOR_N_45	Single-ended: GPIOR_P_31_PLLIN1 Differential: GPIOR_P_31_PLLIN1, GPIOR_N_31	Single-ended: GPIOR_P_44_EXTFB Differential: GPIOR_P_44_EXTFB, GPIOR_N_44
PLL_BR	Single-ended: GPIOR_P_00_PLLIN0 Differential: GPIOR_P_00_PLLIN0, GPIOR_N_00	Single-ended: GPIOR_P_16_PLLIN1 Differential: GPIOR_P_16_PLLIN1, GPIOR_N_16	Single-ended: GPIOR_P_01_EXTFB Differential: GPIOR_P_01_EXTFB, GPIOR_N_01

Table 5. PLL Reference Clock Resource Assignments (G400, G529)
PLL	REFCLK0	REFCLK1	External Feedback I/O
PLL_BL0	Single-ended: GPIOB_P_00_PLLIN0 Differential: GPIOB_P_00_PLLIN0, GPIOB_N_00	Single-ended: GPIOL_00_PLLIN1	Single-ended: GPIOB_P_01_EXTFB Differential: GPIOB_P_01_EXTFB, GPIOB_N_01_CCK
PLL_BL1	Single-ended: GPIOB_P_11_PLLIN0 Differential: GPIOB_P_11_PLLIN0, GPIOB_N_11	Single-ended: GPIOL_10_PLLIN1	Single-ended: GPIOB_P_12_EXTFB Differential: GPIOB_P_12_EXTFB, GPIOB_N_12_SSU_N
PLL_BL2	Single-ended: GPIOB_P_23_PLLIN0 Differential: GPIOB_P_23_PLLIN0, GPIOB_N_23_CDI12	Single-ended: GPIOL_20_PLLIN1	Single-ended: GPIOB_P_24_EXTFB Differential: GPIOB_P_24_EXTFB, GPIOB_N_24_CDI13
PLL_TL0	Single-ended: GPIOT_P_00_PLLIN0 Differential: GPIOT_P_00_PLLIN0, GPIOT_N_00	Single-ended: GPIOL_26_PLLIN1	Single-ended: GPIOT_P_01_EXTFB Differential: GPIOT_P_01_EXTFB, GPIOT_N_01
PLL_TL1	Single-ended: GPIOT_P_11_PLLIN0 Differential: GPIOT_P_11_PLLIN0, GPIOT_N_11	Single-ended: GPIOL_36_PLLIN1	Single-ended: GPIOT_P_12_EXTFB Differential: GPIOT_P_12_EXTFB, GPIOT_N_12
PLL_TL2	Single-ended: GPIOT_P_23_PLLIN0 Differential: GPIOT_P_23_PLLIN0, GPIOT_N_23	Single-ended: GPIOL_32_PLLIN1	Single-ended: GPIOT_P_24_EXTFB Differential: GPIOT_P_24_EXTFB, GPIOT_N_24
PLL_TR	Single-ended: GPIOR_P_45_PLLIN0 Differential: GPIOR_P_45_PLLIN0, GPIOR_N_45	Single-ended: GPIOR_P_31_PLLIN1 Differential: GPIOR_P_31_PLLIN1, GPIOR_N_31	Single-ended: GPIOR_P_44_EXTFB Differential: GPIOR_P_44_EXTFB, GPIOR_N_44
PLL_BR	Single-ended: GPIOR_P_00_PLLIN0 Differential: GPIOR_P_00_PLLIN0, GPIOR_N_00	Single-ended: GPIOR_P_16_PLLIN1 Differential: GPIOR_P_16_PLLIN1, GPIOR_N_16	Single-ended: GPIOR_P_01_EXTFB Differential: GPIOR_P_01_EXTFB, GPIOR_N_01

¹ (M x O x C_FBK) must be ≤ 255.

² There is no dedicated pin assigned to this reference clock.

³ There is no dedicated pin assigned to this reference clock.