Ti180 Driving the Local Network
As described previously, the FPGA has horizontal clock regions. The top and bottom regions are only for the top and bottom interfaces. The other regions are for the core logic (XLR cells, DSP Blocks, and RAM) and the interfaces on the sides.
Local Network for Core Logic
As shown in the following figure, the regions that contain the core logic are 80 XLR cells tall, and the local network connects an area that is 40 XLR cells tall. Additionally, each column has its own local network. For example, in the first column, XLR cells 1 - 40 are in the same local network and XLR cells 41 - 80 are in another local network. DSP Blocks and RAM also have their own local networks. This pattern of block/local network is repeated for each column in the die.
- The global network (32 possible signals)
- The core fabric in another region (16 possible signals)
- The regional network
(four
or
eight
possible signals):
- For the top and bottom regions eight signals can come from the regional network.
- For the other regions, four signals can come from the regional network. (Refer back to Ti180 Clock and Control Network.)
Additionally, the local fabric can generate clock and control signals for the local network. The fabric can also drive the clock enable for the XLR cell directly, allowing each XLR cell to have a unique clock enable.
Local Network for Interface Regions
The following figure shows the local clock networks for the interface blocks. There are a limited number of unique clocks per local clock region.
- The top and bottom regions can each support up to 16 unique clock signals; 14 from the global network and two from the fabric.
- The left and right regions can each support up to four unique clock signals. Up to two can come from the routing fabric, the rest come from the global or regional buffers. These regions are the same height as the core local regions (that is, 40 rows).
