Efinix, Inc.
  • Ti180 Introduction
  • Ti180 Features
    • Ti180 Package-Dependent Resources
    • Ti180 Available Package Options
  • Ti180 Device Core Functional Description
    • Ti180 XLR Cell
    • Ti180 Embedded Memory
      • Ti180 True Dual-Port Mode
      • Ti180 Simple Dual-Port Mode
    • Ti180 DSP Block
    • Ti180 Clock and Control Network
      • Ti180 Clock Sources that Drive the Global and Regional Networks
      • Ti180 Driving the Global Network
      • Ti180 Driving the Regional Network
      • Ti180 Driving the Local Network
  • Ti180 Device Interface Functional Description
    • Ti180 Interface Block Connectivity
    • Ti180 GPIO
      • Ti180 Features for HVIO and HSIO Configured as GPIO
        • Ti180 Double-Data I/O
        • Ti180 Programmable Delay Chains
      • Ti180 HVIO
      • Ti180 HSIO
        • Ti180 HSIO Configured as GPIO
        • Ti180 HSIO Configured as LVDS
        • Ti180 HSIO Configured as MIPI Lane
      • Ti180 I/O Banks
    • Ti180 DDR DRAM Interface
    • Ti180 LPDDR4x SDRAM (J484D1 Only)
    • Ti180 MIPI D-PHY
      • Ti180 MIPI RX D-PHY
      • Ti180 MIPI TX D-PHY
    • Ti180 Oscillator
    • Ti180 PLL
      • Ti180 Dynamic Phase Shift
    • Ti180 Spread-Spectrum Clocking PLL
    • Ti180 Single-Event Upset Detection
    • Ti180 Internal Reconfiguration Block
  • Ti180 Security Feature
  • Ti180 Power Sequence
    • Ti180 Power-Up Sequence
    • Ti180 Power-Down Sequence
    • Ti180 LPDDR4x SDRAM Power Up Requirements
    • Ti180 Power Supply Current Transient
    • Ti180 Unused Resources and Features
  • Ti180 Configuration
    • Ti180 Supported Configuration Modes
  • Ti180 Characteristics and Timing
    • Ti180 DC and Switching Characteristics
    • Ti180 HSIO Electrical and Timing Specifications
    • Ti180 MIPI Electrical Specifications and Timing
      • Ti180 MIPI Reset Timing
    • Ti180 PLL Timing and AC Characteristics
    • Ti180 Configuration Timing
      • Ti180 JTAG Mode
      • Ti180 SPI Active Mode
      • Ti180 SPI Passive Mode
  • Ti180 Pinout Description
    • Ti180 Configuration Pins
    • Ti180 Dedicated DDR Pinout
    • Ti180 Dedicated MIPI D-PHY Pinout
    • Ti180 Pin States
  • Ti180 Interface Floorplan
  • Ti180 Efinity Software Support
  • Ti180 Ordering Codes
  • Ti180 Revision History

Ti180 Power Sequence

Important: You must follow the power-up and power-down sequence when powering Titanium FPGAs.
  • Ti180 Power-Up Sequence
  • Ti180 Power-Down Sequence
  • Ti180 LPDDR4x SDRAM Power Up Requirements
  • Ti180 Power Supply Current Transient
  • Ti180 Unused Resources and Features

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