Ti180 Package-Dependent Resources

Table 1. Ti180 Package-Dependent Resources
Resource J361 G400 J484 J484D1 L484 M484 G529
Single-ended GPIO (Maximum) HVIO
LVCMOS: 1.8, 2.5, 3.0, 3.3 V
LVTTL: 3.0, 3.3 V
 20 74 27 54 27 27 48
HSIO
LVCMOS, HSTL: 1.2, 1.5, 1.8 V
SSTL: 1.2, 1.35, 1.5, 1.8 V
 110 200 116 190 116 116 210
Differential GPIO (Maximum) HSIO (LVDS, Differential HSTL, and SSTL) 54 100 57 94 57 57 105
HSIO (MIPI D-PHY Data Lanes) 45 82 47 79 47 47 88
HSIO (MIPI D-PHY Clock Lanes) 9 17 10 15 10 10 17
LPDDR4/4x PHY with memory controller 1 x16 – 1 x32 1 x16 – 1 x16 1 x32
LPDDR4x SDRAM 2 Gbits, up to 3,000 Mbps data rate, 16-bit data bus – – – – – –
MIPI D-PHY Hard Blocks RX 2 – 4 2 4 4 –
TX or SSC PLL 2 – 4 2 4 4 –
Global clock or control signals from GPIO pins 20 32 32 32 32 32 32
PLLs 8 8 8 8 8 8 8
Note: The x32 LPDDR4/4x PHY with memory controller can be configured as x16 or x32 widths.