Ti180 DC and Switching Characteristics

Table 1. Absolute Maximum Ratings^¹ Conditions beyond those listed may cause permanent damage to the device. Device operation at the absolute maximum ratings for extended periods of time has adverse effects on the device.
Symbol	Description	Min	Max	Units
VCC	Core power supply.	-0.5	1.05	V
VCCA	PLL analog power supply.	-0.5	1.05	V
VCCAUX	1.8 V auxiliary power supply.	-0.5	1.98	V
VQPS	1.8 V security fuse supply.	-0.5	1.98	V
VCCIO	HSIO bank power supply.	-0.5	1.98	V
VCCIO33	HVIO bank power supply.	-0.5	3.63	V
VCC18A_MIPI_TX	1.8 V TX analog power supply for MIPI TX.	-0.5	1.98	V
VCC18A_MIPI_RX	1.8 V TX analog power supply for MIPI RX.	-0.5	1.98	V
VDD_PHY	LPDDR4/4x digital power supply.	-0.5	1.05	V
VDDPLL_MCB_TOP_PHY	LPDDR4/4x PLL power supply.	-0.5	1.05	V
VDDQ_PHY	LPDDR4/4x I/O power supply.	-0.5	1.21	V
VDDQX_PHY	LPDDR4/4x I/O pre-driver power supply.	-0.5	1.21	V
VDDQ_CK_PHY	LPDDR4/4x I/O power supply for clock.	-0.5	1.21	V
VDD1	Core 1 power for LPDDR4x SDRAM. J484D1 packages only.	-0.4	2.1	V
VDD2	Core 2 power/input buffer for LPDDR4x SDRAM. J484D1 packages only.	-0.4	1.5	V
VDDQ	I/O buffer power for LPDDR4x SDRAM. J484D1 packages only.	-0.4	1.5	V
I_IN	Maximum current allowed through any I/O pin when the device is not turned on or during power-up/down with forward biasing of the clamp diode.²	–	10	mA
V_IN	HVIO input voltage.	-0.5	3.63	V
V_IN	HSIO input voltage.	-0.5	1.98	V
T_J	Operating junction temperature. (All other packages)	-40	125	°C
T_J	Operating junction temperature. (J484D1 packages only)	-40	105³	°C
T_STG	Storage temperature, ambient.	-55	150	°C

Table 2. Recommended Operating Conditions ^¹
Symbol	Description	Min	Typ	Max	Units
VCC	C3L, C4L, I3L, I4L speed grade core power supply.	0.82	0.85	0.88	V
VCC	C3, C4, I3, I4, Q3 speed grade core power supply.	0.92	0.95	0.98	V
VCCA	C3L, C4L, I3L, I4L speed grade PLL analog power supply.	0.82	0.85	0.88	V
VCCA	C3, C4, I3, I4, Q3 speed grade PLL analog power supply.	0.92	0.95	0.98	V
VCCAUX	1.8 V auxiliary power supply.	1.75	1.8	1.85	V
VQPS	1.8 V security fuse supply.	1.71	1.8	1.89	V
VCCIO	1.2 V HSIO bank power supply.	1.14	1.2	1.26	V
	1.35 V HSIO bank power supply	1.283	1.35	1.417	V
	1.5 V HSIO bank power supply.	1.425	1.5	1.575	V
	1.8 V HSIO bank power supply.	1.71	1.8	1.89	V
VCCIO33	1.8 V HVIO bank power supply.	1.71	1.8	1.89	V
	2.5 V HVIO bank power supply.	2.375	2.5	2.625	V
	3.0 V HVIO bank power supply.	2.85	3.0	3.15	V
	3.3 V HVIO bank power supply.	3.135	3.3	3.465	V
VCC18A_MIPI_TX	1.8 V analog power supply for MIPI TX.	1.71	1.8	1.89	V
VCC18A_MIPI_RX	1.8 V analog power supply for MIPI RX.	1.71	1.8	1.89	V
VDD_PHY	LPDDR4/4x digital power supply.	0.82	0.85	0.88	V
VDDPLL_MCB_TOP_PHY	LPDDR4/4x PLL power supply.	0.82	0.85	0.88	V
VDDQ_PHY	LPDDR4 I/O power supply. ^⁴	1.06	1.1	1.17	V
VDDQ_PHY	LPDDR4x I/O power supply.	0.57	0.6	0.65	V
VDDQX_PHY	LPDDR4 I/O pre-driver power supply.^⁴	1.06	1.1	1.17	V
VDDQX_PHY	LPDDR4x I/O pre-driver power supply.	1.06	1.1	1.17	V
VDDQ_CK_PHY	LPDDR4 I/O power supply for clock.^⁴	1.06	1.1	1.17	V
VDDQ_CK_PHY	LPDDR4x I/O power supply for clock.	0.57	0.6	0.65	V
VDD1	Core 1 power for LPDDR4x SDRAM. J484D1 packages only.	1.70	1.80	1.95	V
VDD2	Core 2 power/input buffer for LPDDR4x SDRAM. J484D1 packages only.	1.06	1.10	1.17	V
VDDQ	I/O buffer power for LPDDR4x SDRAM. J484D1 packages only.	0.57	0.6	0.65	V
T_JCOM	Operating junction temperature, commercial.	0	–	85	°C
T_JIND	Operating junction temperature, industrial.	-40	–	100	°C
T_JAUTO	Operating junction temperature, automotive.	-40	–	125	°C

Table 3. Power Supply Ramp Rates
Symbol	Description	Min	Max	Units
t_RAMP	Power supply ramp rate for all supplies.	0.1 * V_supply	10	V/ms

Table 4. HVIO DC Electrical Characteristics
I/O Standard	V_IL (V)		V_IH (V)		V_OL (V)	V_OH (V)
I/O Standard	Min	Max	Min	Max	Max	Min
3.3 V LVCMOS	-0.3	0.8	2.1	3.465	0.2	VCCIO33 - 0.2
3.0 V LVCMOS	-0.3	0.8	2.1	3.15	0.2	VCCIO33 - 0.2
3.3 V LVTTL	-0.3	0.8	2.1	3.465	0.4	2.4
3.0 V LVTTL	-0.3	0.8	2.1	3.15	0.4	2.4
2.5 V LVCMOS	-0.3	0.45	1.7	2.625	0.4	2.0
1.8 V LVCMOS	-0.3	0.58	1.27	1.89	0.45	VCCIO33 - 0.45
1.8 V LVCMOS (JTAG)⁵	-0.3	0.28	1.27	1.89	0.45	VCCIO33 - 0.45

Table 5. HVIO DC Electrical Characteristics
Voltage (V)	Typical Hysteresis (mV)⁶	Input Leakage Current (`μ`A)	Tristate Output Leakage Current (`μ`A)
3.3	250	±25	±10
2.5	250	±25	±10
1.8	200	±25	±10

Table 6. HSIO Pins Configured as Single-Ended I/O DC Electrical Characteristics
I/O Standard	V_IL (V)		V_IH (V)		V_OL (V)	V_OH (V)
I/O Standard	Min	Max	Min	Max	Max	Min
1.8 V LVCMOS	-0.3	0.58	1.27	1.89	0.45	VCCIO - 0.45
1.5 V LVCMOS	-0.3	0.35 * VCCIO	0.65 * VCCIO	1.575	0.25 * VCCIO	0.75 * VCCIO
1.2 V LVCMOS	-0.3	0.35 * VCCIO	0.65 * VCCIO	1.26	0.25 * VCCIO	0.75 * VCCIO
1.8 V HSTL	–	VREF - 0.1	VREF + 0.1	–	0.4	VCCIO - 0.4
1.5 V HSTL	–	VREF - 0.1	VREF + 0.1	–	0.4	VCCIO - 0.4
1.2 V HSTL	-0.15	VREF - 0.08	VREF + 0.08	VREF + 0.15	0.25 * VCCIO	0.75 * VCCIO
1.8 V SSTL	-0.3	VREF - 0.125	VREF + 0.125	VCCIO + 0.3	VTT - 0.603	VTT + 0.603
1.5 V SSTL	–	VREF - 0.1	VREF + 0.1	–	0.2 * VCCIO	0.8 * VCCIO
1.35 V SSTL	–	VREF - 0.1	VREF + 0.1	–	0.2 * VCCIO	0.8 * VCCIO
1.2 V SSTL	–	VREF - 0.1	VREF + 0.1	–	0.2 * VCCIO	0.8 * VCCIO

Table 7. HSIO Pins Configured as Single-Ended I/O DC Electrical Characteristics
I/O Standard	VREF (V)			Vtt (V)
I/O Standard	Min	Typ	Max	Min	Typ	Max
1.8 V HSTL	0.85	0.9	0.95	–	0.5 * VCCIO	–
1.5 V HSTL	0.68	0.75	0.9	–	0.5 * VCCIO	–
1.2 V HSTL	0.47 * VCCIO	0.5 * VCCIO	0.53 * VCCIO	–	0.5 * VCCIO	–
1.8 V SSTL	0.833	0.9	0.969	VREF - 0.04	VREF	VREF + 0.04
1.5 V SSTL	0.49 * VCCIO	0.5 * VCCIO	0.51 * VCCIO	0.49 * VCCIO	0.5 * VCCIO	0.51 * VCCIO
1.35 V SSTL	0.49 * VCCIO	0.5 * VCCIO	0.51 * VCCIO	0.49 * VCCIO	0.5 * VCCIO	0.51 * VCCIO
1.2 V SSTL	0.49 * VCCIO	0.5 * VCCIO	0.51 * VCCIO	0.49 * VCCIO	0.5 * VCCIO	0.51 * VCCIO

Table 8. HSIO Pins Configured as Differential SSTL I/O Electrical Characteristics
I/O Standard	V_{SWING (DC)} (V)		V_X(AC) (V)			V_{SWING (AC)} (V)
I/O Standard	Min	Max	Min	Typ	Max	Min	Max
1.8 V SSTL	0.25	VCCIO + 0.6	VCCIO/2 – 0.175	–	VCCIO/2 + 0.175	0.5	VCCIO + 0.6
1.5 V SSTL	0.2	–	VCCIO/2 – 0.15	–	VCCIO/2 + 0.15	0.35	–
1.35 V SSTL	0.2	–	VCCIO/2 – 0.15	–	VCCIO/2 + 0.15	0.35	–
1.2 V SSTL	0.18	–	VREF– 0.15	VCCIO /2	VREF + 0.15	-0.3	0.3

Table 9. HSIO Pins Configured as Differential HSTL I/O Electrical Characteristics
I/O Standard	V_{DIF (DC)} (V)		V_{X (AC)} (V)			V_{CM (DC)} (V)			V_{DIF (AC)} (V)
I/O Standard	Min	Max	Min	Typ	Max	Min	Typ	Max	Min	Max
1.8 V HSTL	0.2	–	0.78	–	1.12	0.78	–	1.12	0.4	–
1.5 V HSTL	0.2	–	0.68	–	0.9	0.68	–	0.9	0.4	–
1.2 V HSTL	0.16	VCCIO + 0.3	–	0.5 * VCCIO	–	0.4 * VCCIO	0.5 * VCCIO	0.6 * VCCIO	0.3	VCCIO + 0.48

Table 10. HSIO Pins Configured as Single-Ended I/O DC Electrical Characteristics
Voltage (V)	Typical Hysteresis (mV)⁷	Input Leakage Current (`μ`A)	Tristate Output Leakage Current (`μ`A)
1.8	200	±25	±10
1.5	160	±25	±10
1.35	–	±25	±10
1.2	140	±25	±10

Table 11. Supported HVIO Drive Strength
I/O Standard	Drive Strength	Units
3.3 V LVTTL	4, 8, 12, 16	mA
3.3 V LVCMOS	2, 4, 6, 8	mA
3.0 V LVTTL	4, 8, 12, 16	mA
3.0 V LVCMOS	2, 4, 6, 8	mA
2.5 V LVCMOS	4, 8, 12, 16	mA
1.8 V LVCMOS	4, 8, 12, 16	mA

Table 12. Supported HSIO Drive Strength
I/O Standard	Drive Strength	Units
1.8 V LVCMOS	4, 8, 12, 16	mA
1.5 V LVCMOS	4, 8, 12, 16	mA
1.2 V LVCMOS	2, 4, 8, 12	mA
1.8 V SSTL	4, 8, 10, 12	mA
1.5 V SSTL	4, 8, 10, 12	mA
1.35 V SSTL	4, 8, 10, 12	mA
1.2 V SSTL	4, 8, 10, 12	mA
1.8 V HSTL	4, 8, 10, 12	mA
1.5 V HSTL	4, 8, 10, 12	mA
1.2 V HSTL	4, 8, 10, 12	mA

Table 13. Maximum Toggle Rate
I/O	I/O Standard	Speed Grade	Serialization Mode	Max Toggle Rate (Mbps)⁸ ⁹
HVIO	3.0 V, 3.3 V LVTTL 3.0 V, 3.3 V LVCMOS	All	–	200
HVIO	2.5 V LVCMOS	All	–	100
HVIO	1.8 V LVCMOS	All	–	400
HSIO	1.8 V, 1.5 V, 1.2 V LVCMOS	All	–	400
HSIO	1.8 V, 1.5 V, 1.35 V, 1.2 V SSTL 1.8 V, 1.5 V, 1.2 V HSTL	All	–	800
HSIO	LVDS	C4, I3, I4, Q3	Full-rate	1,000
		C4, I3, I4, Q3	Half-rate	1,500
		C3	Full-rate	1,000
		C3	Half-rate	1,300
		C4L, I3L, I4L	Full-rate	800
		C4L, I3L, I4L	Half-rate	1,250
		C3L	Full-rate	800
		C3L	Half-rate	1,100
HSIO	Sub-LVDS	C3, C4, I3, I4, Q3	Full-rate	1,000
		C3, C4, I3, I4, Q3	Half-rate	1,250
		C3L, C4L, I3L, I4L	Full-rate	800
		C3L, C4L, I3L, I4L	Half-rate	1,250
HSIO	MIPI lane	C4, I3, I4, Q3	–	1,500
		C3	–	1,300
		I3L, C4L, I4L	–	1,250
		C3L	–	1,100

Table 14. HVIO Internal Weak Pull-Up and Pull-Down Resistance
I/O Standard	Internal Pull-Up			Internal Pull-Down			Units
I/O Standard	Min	Typ	Max	Min	Typ	Max	Units
3.3 V LVTTL/LVCMOS	25	42	67	24	29	33	kΩ
3.0 V LVTTL/LVCMOS	25	42	67	24	29	33	kΩ
2.5 V LVCMOS	25	42	67	24	29	33	kΩ
1.8 V LVCMOS	25	35	45	24	29	33	kΩ

Table 15. HSIO Internal Weak Pull-Up and Pull-Down ResistanceCDONE and CRESET_N also have an internal weak pull-up with these values.
I/O Standard	Speed Grade	Internal Pull-Up			Internal Pull-Down			Units
I/O Standard	Speed Grade	Min	Typ	Max	Min	Typ	Max	Units
1.8 V LVCMOS, HSTL, SSTL	C3, C4, I3, C3L, C4L, I3L	18	27	47	18	27	47	kΩ
1.8 V LVCMOS, HSTL, SSTL	Q3	15	27	47	15	27	47	kΩ
1.5 V LVCMOS, HSTL, SSTL	C3, C4, I3, C3L, C4L, I3L	22	38	65	22	38	65	kΩ
1.5 V LVCMOS, HSTL, SSTL	Q3	20	38	65	20	38	65	kΩ
1.35 V SSTL	C3, C4, I3, C3L, C4L, I3L	30	52	100	30	52	100	kΩ
1.35 V SSTL	Q3	22	52	100	22	52	100	kΩ
1.2 V LVCMOS, HSTL, SSTL	C3, C4, I3, C3L, C4L, I3L	40	66	135	40	66	135	kΩ
1.2 V LVCMOS, HSTL, SSTL	Q3	25	66	135	25	66	135	kΩ

Table 16. Single-Ended I/O Programmable Delay Chain Step Size: Static
Speed Grade	Delay per Step			Units
Speed Grade	Min	Typ	Max	Units
C3, C4, I3, I4, Q3	35	55	75	ps
C3L, C4L, I3L, I4L	50	68	89	ps

Table 17. Single-Ended I/O Programmable Delay Chain Step Size: Dynamic
Speed Grade	Delay per Step			Units
Speed Grade	Min	Typ	Max	Units
C3, C4, I3, I4	12	18	24	ps
Q3	12	18	26	ps
C3L, C4L, I3L, I4L	15	22	28	ps

Table 18. Differential I/O Programmable Delay Chain Step Size: Static and Dynamic
Speed Grade	Delay per Step			Units
Speed Grade	Min	Typ	Max	Units
C3, C4, I3, I4	12	18	24	ps
Q3	12	18	26	ps
C3L, C4L, I3L, I4L	15	22	28	ps

Table 19. Block RAM, DSP Block, Gobal Clock Buffer, and DPA Performance
Description	Speed Grade			Units
Description	C3, C4, I3, I4	Q3	C3L, C4L, I3L, I4L	Units
Block RAM maximum frequency.	1,000	900	800	MHz
DSP block maximum frequency.	1,000	900	800	MHz
Global clock buffer block maximum frequency.	1,000	1,000	800	MHz
DPA maximum data rate.	1,000	1,000	800	Mbps

Table 20. MIPI D-PHY Interface Performance
Description	Packages	FPGA Speed Grade				Units
Description	Packages	C4, I3	C3, I4	C3L, C4L, I3L, I4L	Q3	Units
MIPI D-PHY block maximum data rate.	J361, L484, M484	2.5	2.5	2.0	–	Gbps
	J484	2.5	2.5	2.0	2.0	Gbps
	J484D1	2.5	–	–	–	Gbps

Table 21. LPDDR4/4x Interface Performance
Description	Packages	FPGA Speed Grade					Units
Description	Packages	C4	I4, C4L, I4L	I3	C3, C3L, I3L	Q3	Units
LPDDR4/4x DRAM interface maximum data rate.	M484	2.6	2.6	2.0	2.0	–	Gbps
	J361	3.0	3.0	2.5	2.5	–	Gbps
	J484	3.0	3.0	2.5	2.5	2.5	Gbps
	G529	3.3	3.3	2.8	2.8	–	Gbps
LPDDR4x DRAM interface maximum data rate.	J484D1	3.0	–	2.5	–	–	Gbps

Table 22. V_IH, V_IL, V_OL, and V_OH Specifications for LPDDR4/4x
Description	V_IL (V)		V_IH (V)		V_OL (V)	V_OH (V)
Description	Min	Max	Min	Max	Max	Min
LPDDR4	–	(V_{DDQ_PHY} / 6) - 0.075	(V_{DDQ_PHY} / 6) + 0.075	–	V_{DDQ_PHY} * 0.1	V_{DDQ_PHY} * 0.5
LPDDR4x	–	(V_{DDQ_PHY} / 4) - 0.075	(V_{DDQ_PHY} / 4) + 0.075	–	V_{DDQ_PHY} * 0.1	V_{DDQ_PHY} * 0.5

¹ Supply voltage specification applied to the voltage taken at the device pins with respect to ground, not at the power supply.

² Should not exceed a total of 100 mA per bank

³ This temperature is the maximum for the LPDDR4x DRAM.

⁴ Not applicable to J484D1 packages.

⁵ For JTAG configuration mode

⁶ For input pins with Schmitt Trigger enabled

⁷ For LVCMOS input pins with Schmitt Trigger enabled

⁸ The maximum toggle rate is dependent on the drive strength and external load conditions. Perform IBIS simulation to determine the optimal drive strength setting to achieve the targeted toggle rate.

⁹ All I/O standards are characterized with 5 pF load, except for LVTTL and LVCMOS standards which are characterized with 15 pF load.