Ti180 LPDDR4x SDRAM Power Up Requirements

Note: These requirements only apply to J484D1 packages.
The following table shows the power supply voltage ramp rates for the LPDDR4x SDRAM device.
  • VDD1 must ramp at the same time or earlier than VDD2.
  • VDD2 must ramp at the same time or earlier than VDDQ.
Figure 1. LPDDR4x SDRAM Power Supply Ramp Up Sequence
Table 1. LPDDR4x Voltage Ramp Conditions
After Applicable Condition
tA is reached VDD1 must be greater than VDD2.
VDD2 must be greater than VDDQ - 200 mV.
Notes:
  • tA is the point at which any power supply first reaches 300 mV.
  • These voltage ramp conditions apply between tA and power-off (controlled or uncontrolled).
  • tB is the point at which all supply and reference voltages are within their defined ranges.
  • The power ramp duration tINIT0 (tB - tA) must not exceed 20 ms.
Notice: Refer to the JEDEC standard for other detailed requirements on LPDDR4x-related power-up and power-down sequences.