Ti180 LPDDR4x SDRAM (J484D1 Only)

The Ti180J484D1 FPGA includes an LPDDR4x SDRAM device in the package. The DRAM has a density of 2 Gbits and a clock rate of up to 1,500 MHz. It supports double-data rates of up to 3,000 Mbps and has a 16-bit data bus.

Figure 1. LPDDR4x SDRAM Interface Block Diagram
Note: The PLL reference clock must be driven by I/O pads. The Efinity software issues a warning if you do not connect the reference clock to an I/O pad. (Using the clock tree may induce additional jitter and degrade the DDR performance.) Refer to Ti180 PLL for more information about the PLL block.
Table 1. LPDDR4X Pad
Name Direction Description
ZQ Input Calibration resistor pin. This pin calibrates the drive strength and termination resistance. Connect the ZQ pin to VDDQ through a 240 Ω ± 1% resistor.