Introduction

The BRAM Wrapper core utilizes the embedded block memory within the FPGA to optimize the utilization of memory primitives. It can be configured as Single-port RAM, Simple Dual-port RAM, True Dual-port RAM, Single-port ROM, or True Dual-port ROM. The BRAM Wrapper consists of Port A and Port B, which serve as the write and read interfaces within a shared memory space, offering a wide range of configurations.

Use the IP Manager to select IP, customize it, and generate files. The BRAM Wrapper core has an interactive wizard to help you set parameters. The wizard also has options to create a testbench and/or example design targeting an Efinix® development board.