Resource Utilization and Performance

Note: The resources and performance values provided are based on some of the supported FPGAs. These values are just guidance and may change depending on the device resource utilization, design congestion, and user design.
Each memory type are tested with the following settings:
  • Single-port RAM and Single-port ROM—512-bit data width and 512 depth
  • Simple Dual-port RAM—256-bit data width and 256 depth
  • True Dual-port RAM and Dual-port ROM—128-bit data width and 128 depth
Note: Slight fluctuation in the performance frequency may occur after you changed the pipeline configuration and re-synthesize the design. This is due to the Efinity random Placement and Routing behavior when you re-synthesize the design.

Titanium Resource Utilization and Performance

Table 1. Synchronous Clock BRAM Wrapper
FPGA Memory Type Width Ratio Output Pipeline Register Logic Elements 1 Memory Blocks DSP Blocks fMAX (MHz) clk Efinity Version
Ti60 F225 C4 SP RAM 1:1 Disable 0/62016 (0%) 26/256 (10%) 0/160 (0%) 638 2023.1
Enable 0/62016 (0%) 26/256 (10%) 0/160 (0%) 1010
SDP RAM 1:1 Disable 0/62016 (0%) 13/256 (5%) 0/160 (0%) 635
Enable 0/62016 (0%) 13/256 (5%) 0/160 (0%) 1028
1:2 Disable 0/62016 (0%) 32/256 (12%) 0/160 (0%) 642
Enable 0/62016 (0%) 32/256 (12%) 0/160 (0%) 1024
TDP RAM 1:1 Disable 0/62016 (0%) 13/256 (5%) 0/160 (0%) 659
Enable 0/62016 (0%) 13/256 (5%) 0/160 (0%) 1111
1:2 Disable 0/62016 (0%) 32/256 (12%) 0/160 (0%) 642
Enable 0/62016 (0%) 32/256 (12%) 0/160 (0%) 950
SP ROM 1:1 Disable 0/62016 (0%) 26/256 (10%) 0/160 (0%) 660
Enable 0/62016 (0%) 26/256 (10%) 0/160 (0%) 1054
DP ROM 1:1 Disable 0/62016 (0%) 13/256 (5%) 0/160 (0%) 1113
Enable 0/62016 (0%) 13/256 (5%) 0/160 (0%) 1116
1:2 Disable 0/62016 (0%) 32/256 (12%) 0/160 (0%) 1015
Enable 0/62016 (0%) 32/256 (12%) 0/160 (0%) 1033
Table 2. Asynchronous Clock BRAM Wrapper (True Dual-port RAM and Dual-port ROM)
clk_a/b in True Dual-port RAM is for simultaneous write and read operation for each respective port.
clk_a/b in Dual-port ROM is for read operation only for each respective port.
FPGA Memory Type Width Ratio Output Pipeline Register Logic Elements1 Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
clk_a clk_b
Ti60 F225 C4 TDP RAM 1:1 Disable 0/62016 (0%) 13/256 (5%) 0/160 (0%) 682 656 2023.1
Enable 0/62016 (0%) 13/256 (5%) 0/160 (0%) 1082 1082
1:2 Disable 0/62016 (0%) 32/256 (12%) 0/160 (0%) 670 657
Enable 0/62016 (0%) 32/256 (12%) 0/160 (0%) 961 998
DP ROM 1:1 Disable 0/62016 (0%) 13/256 (5%) 0/160 (0%) 1011 1177
Enable 0/62016 (0%) 13/256 (5%) 0/160 (0%) 1097 1129
1:2 Disable 0/62016 (0%) 32/256 (12%) 0/160 (0%) 982 1048
Enable 0/62016 (0%) 32/256 (12%) 0/160 (0%) 1028 1053
Table 3. Asynchronous Clock BRAM Wrapper (Simple Dual-port RAM)
FPGA Memory Type Width Ratio Output Pipeline Register Logic Elements1 Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
wclk rclk
Ti60 F225 C4 SDP RAM 1:1 Disable 0/62016 (0%) 13/256 (5%) 0/160 (0%) 1000 662 2023.1
Enable 0/62016 (0%) 13/256 (5%) 0/160 (0%) 1000 1094
1:2 Disable 0/62016 (0%) 32/256 (12%) 0/160 (0%) 1000 641
Enable 0/62016 (0%) 32/256 (12%) 0/160 (0%) 1000 1002

Trion Resource Utilization and Performance

Table 4. Synchronous Clock BRAM Wrapper
FPGA Memory Type Width Ratio Output Pipeline Register Logic Elements 1 Memory Blocks DSP Blocks fMAX (MHz) clk Efinity Version
T120 F576 C4 SP RAM 1:1 Disable 0/112128 (0%) 52/1056 (5%) 0/320 (0%) 219 2023.1
Enable 0/112128 (0%) 52/1056 (5%) 0/320 (0%) 306
SDP RAM 1:1 Disable 0/112128 (0%) 13/1056 (1%) 0/320 (0%) 229
Enable 0/112128 (0%) 13/1056 (1%) 0/320 (0%) 327
1:2 Disable 0/112128 (0%) 32/1056 (3%) 0/320 (0%) 222
Enable 0/112128 (0%) 32/1056 (3%) 0/320 (0%) 345
TDP RAM 1:1 Disable 0/112128 (0%) 4/1056 (1%) 0/320 (0%) 264
Enable 0/112128 (0%) 4/1056 (1%) 0/320 (0%) 383
1:2 Disable 0/112128 (0%) 32/1056 (3%) 0/320 (0%) 229
Enable 0/112128 (0%) 32/1056 (3%) 0/320 (0%) 356
SP ROM 1:1 Disable 0/112128 (0%) 26/1056 (2%) 0/320 (0%) 229
Enable 0/112128 (0%) 26/1056 (2%) 0/320 (0%) 342
DP ROM 1:1 Disable 0/112128 (0%) 13/1056 (1%) 0/320 (0%) 235
Enable 0/112128 (0%) 13/1056 (1%) 0/320 (0%) 383
1:2 Disable 0/112128 (0%) 32/1056 (3%) 0/320 (0%) 216
Enable 0/112128 (0%) 32/1056 (3%) 0/320 (0%) 342
Table 5. Asynchronous Clock BRAM Wrapper (True Dual-port RAM and Dual-port ROM)
clk_a/b in True Dual-port RAM is for simultaneous write and read operation for each respective port.
clk_a/b in Dual-port ROM is for read operation only for each respective port.
FPGA Memory Type Width Ratio Output Pipeline Register Logic Elements1 Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
clk_a clk_b
T120 F576 C4 TDP RAM 1:1 Disable 0/112128 (0%) 13/1056 (1%) 0/320 (0%) 237 223 2023.1
Enable 0/112128 (0%) 13/1056 (1%) 0/320 (0%) 404 383
1:2 Disable 0/112128 (0%) 32/1056 (3%) 0/320 (0%) 254 221
Enable 0/112128 (0%) 32/1056 (3%) 0/320 (0%) 377 330
DP ROM 1:1 Disable 0/112128 (0%) 13/1056 (1%) 0/320 (0%) 250 239
Enable 0/112128 (0%) 13/1056 (1%) 0/320 (0%) 390 355
1:2 Disable 0/112128 (0%) 32/1056 (3%) 0/320 (0%) 250 229
Enable 0/112128 (0%) 32/1056 (3%) 0/320 (0%) 379 334
Table 6. Asynchronous Clock BRAM Wrapper (Simple Dual-port)
FPGA Memory Type Width Ratio Output Pipeline Register Logic Elements1 Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
wclk rclk
T120 F576 C4 SDP RAM 1:1 Disable 0/112128 (0%) 13/1056 (1%) 0/320 (0%) 478 219 2023.1
Enable 0/112128 (0%) 13/1056 (1%) 0/320 (0%) 493 330
1:2 Disable 0/112128 (0%) 32/1056 (3%) 0/320 (0%) 389 225
Enable 0/112128 (0%) 32/1056 (3%) 0/320 (0%) 401 331
1 Logic, Adders, Flipflops, etc.