Ports
| Port | Direction | Clock Domain | Description |
|---|---|---|---|
| clk | Input | – | Clock input. |
| we | Input | clk | Write-enable input. |
| re | Input | clk | Read-enable input. |
| wdata_a[Data Width A-1:0] | Input | clk | Write data input. |
| rdata_a[Data Width A-1:0] | Output | clk | Read data output. |
| addr[Address Width A-1:0] | Input | clk | Address input. |
| byteen[(Data Width A/8)-1:0] | Input | clk | Byteen input. This pin is responsible to mask off a byte of data for each bit. The minimum byteen bus width is 1. |
| reset | Input | clk | Reset pin. Applicable to Titanium FPGAs only. |
| addren | Input | clk | Enable or disable Address Update operation. Applicable to Titanium FPGAs only. |
| Port | Direction | Clock Domain | Description |
|---|---|---|---|
| clk | Input | – | Clock input for Single-clock mode. |
| wclk | Input | – | Write clock input for Dual-Clock Mode. |
| byteen [(Data Width A/8)-1:0] | Input | clk/wclk | Byteen input. The minimum byteen bus width is 1. |
| we | Input | clk/wclk | Write-enable input. |
| waddr[(Address Width A-1):0] | Input | clk/wclk | Write address input. |
| wdata_a[(Data Width A-1:0] | Input | clk/wclk | Write data input. |
| rclk | Input | – | Read clock input for Dual-Clock Mode. |
| re | Input | clk/rclk | Read-enable input. |
| raddr[Address Width B-1:0] | Input | clk/rclk | Read address input. |
| rdata_b[Data Width B-1:0] | Output | clk/rclk | Read data output. |
| reset | Input | clk/rclk | Reset pin. Applicable to Titanium FPGAs only. |
| waddren | Input | clk/wclk | Enable or disable write Address Update operation. Applicable to Titanium FPGAs only. |
| raddren | Input | clk/rclk | Enable or disable read Address Update operation. Applicable to Titanium FPGAs only. |
| Port | Direction | Clock Domain | Description |
|---|---|---|---|
| clk | Input | – | Clock input in single-clock mode. |
| clk_a | Input | – | Clock input for Port A in dual-clock mode. |
| byteen_a | Input | clk/clk_a | ByteEnable input for Port A. |
| we_a | Input | clk/clk_a | Write-enable for Port A. |
| addr_a[(Address Width A-1):0] | Input | clk/clk_a | Write and read address input for Port A. |
| wdata_a[(Data Width A-1:0] | Input | clk/clk_a | Write data input for Port A. |
| rdata_a[(Data Width A-1:0] | Output | clk/clk_a | Read data output for Port A. |
| clk_b | Input | – | Clock input for Port B in dual-clock mode. |
| byteen_b | Input | clk/clk_b | ByteEnable input for Port B. |
| we_b | Input | clk/clk_b | Write-enable for Port B. |
| addr_b[(Address Width B-1):0] | Input | clk/clk_b | Write and read address input for Port B. |
| wdata_b[(Data Width B-1:0] | Input | clk/clk_b | Write data input for Port B. |
| rdata_b[(Data Width B-1:0] | Output | clk/clk_b | Read data output for Port B. |
| reset_a | Input | clk/clk_a | Reset for Port A. Applicable to Titanium FPGAs only. |
| addren_a | Input | clk/clk_a | Enable or disable write Address Update operation via Port A. Applicable to Titanium FPGAs only. |
| reset_b | Input | clk/clk_b | Reset for Port B. Applicable to Titanium FPGAs only. |
| addren_b | Input | clk/clk_b | Enable or disable write Address Update operation via Port B. Applicable to Titanium FPGAs only. |
| Port | Direction | Clock Domain | Description |
|---|---|---|---|
| clk | Input | – | Clock input for single-clock mode. |
| re | Input | clk | Read-enable input. |
| rdata_a[Data Width A-1:0] | Output | clk | Read data output. |
| addr[Address Width A-1:0] | Input | clk | Address input. |
| reset | Input | clk | Reset pin. Applicable to Titanium FPGAs only. |
| addren | Input | clk | Enable or disable Address Update operation. Applicable to Titanium FPGAs only. |
| Port | Direction | Clock Domain | Description |
|---|---|---|---|
| clk | Input | – | Clock input in one clock mode. |
| clk_a | Input | – | Clock input for Port A in dual clock mode. |
| addr_a[(Address Width A-1):0] | Input | clk/clk_a | Write and read address input for Port A. |
| rdata_a[(Data Width A-1:0] | Output | clk/clk_a | Read data output for Port A. |
| clk_b | Input | – | Clock input for Port B in dual clock mode. |
| addr_b[(Address Width B-1):0] | Input | clk/clk_b | Write and read address input for Port B. |
| rdata_b[(Data Width B-1:0] | Output | clk/clk_b | Read data output for Port B. |
| reset_a | Input | clk/clk_a | Reset for Port A. Applicable to Titanium FPGAs only. |
| addren_a | Input | clk/clk_a | Enable or disable write Address Update operation via Port A. Applicable to Titanium FPGAs only. |
| reset_b | Input | clk/clk_b | Reset for Port B. Applicable to Titanium FPGAs only. |
| addren_b | Input | clk/clk_b | Enable or disable write Address Update operation via Port B. Applicable to Titanium FPGAs only. |