Conflict Resolution

The True Dual-port RAM can perform two write operations to the same memory location for both data from port A and port B. Accessing the same memory location from both ports in the same clock cycle will cause address collisions. There is no internal circuitry to prevent this conflict. Therefore, user must resolve it externally during configuration to prevent unknown data being written to the address.

The following table illustrates the Read Data Port A, Read Data Port B outcome and the resulting RAM content based on Write Mode [A|B] and Write Enable [A|B] configuration.

Table 1. Resulting RAM Content based on Write Mode[A|B] and Write Enable[A|B]
Write Enable[A|B] = 1 : Simultaneous Write and Read
Write Enable[A|B] = 0 : Read only
Write Mode Port A Write Mode Port B Write Enable Port A Write Enable Port B Read Data Port A Read Data Port B Resulting RAM content
Read First Read First 0 0 Valid Valid Valid
0 1 Valid Valid Valid
1 0 Valid Valid Valid
1 1 Valid Valid Unknown
Read First Write First 0 0 Valid Valid Valid
0 1 Valid Valid Valid
1 0 Valid Valid Valid
1 1 Valid Valid Unknown
Read First No Change 0 0 Valid Valid Valid
0 1 Valid Valid Valid
1 0 Valid Valid Valid
1 1 Valid Valid Unknown
Write First Read First 0 0 Valid Valid Valid
0 1 Valid Valid Valid
1 0 Valid Valid Valid
1 1 Valid Valid Unknown
Write First Write First 0 0 Valid Valid Valid
0 1 Valid Valid Valid
1 0 Valid Valid Valid
1 1 Valid Valid Unknown
Write First No Change 0 0 Valid Valid Valid
0 1 Valid Valid Valid
1 0 Valid Valid Valid
1 1 Valid Valid Unknown
No Change Read First 0 0 Valid Valid Valid
0 1 Valid Valid Valid
1 0 Valid Valid Valid
1 1 Valid Valid Unknown
No Change Write First 0 0 Valid Valid Valid
0 1 Valid Valid Valid
1 0 Valid Valid Valid
1 1 Valid Valid Unknown
No Change No Change 0 0 Valid Valid Valid
0 1 Unknown Valid Valid
1 0 Valid Unknown Valid
1 1 Valid Valid Unknown