Memory Modes

The BRAM Wrapper core supports area-optimized and speed-optimized modes for all RAM and ROM.

Table 1. BRAM Wrapper Memory Modes
Memory Mode	Description
Area-Optimized	Utilizes a minimum number of block RAM Performance slightly lower than speed-optimized mode Supported in symmetrical port width configuration only
Speed-Optimized	Utilizes a minimal number of multiplexers, address encoder logic, and fanout for better performance Costs more embedded block memory resources Supported in symmetrical and asymmetrical port width configuration

The following table shows the logic utilization and f_MAX comparison of a design with the memory mode set to area-optimized and speed-optimized. The design uses the default BRAM Wrapper core parameters except for the BRAM Depth which is set to 8192.

Table 2. Area vs. Speed Optimization
FPGA	Memory Type	Memory Mode	Logic Elements	Memory Blocks	f_MAX (MHz)	Efinity Version
Ti60 F225 C4	SDP RAM	Area	36/62016 (1%)	13/256 (5%)	536	2023.1
Ti60 F225 C4	SDP RAM	Speed	0/62016 (0%)	16/256 (6%)	648	2023.1

Note: You may not notice significant performance differences in designs that use smaller BRAM Depth. Generally, the higher the BRAM Depth, the greater the performance differences tend to be.