BRAM Wrapper Example Design

You can choose to generate the example design when generating the core in the IP Manager Configuration window. Compile the example design project and download the .hex or .bit file to your board. To generate example design, the Example Design Deliverables Option signal must be enabled.

Important: tested the example design generated with the default parameter options only.

The example design targets Titanium Ti60 F225 and Trio T120 F576 Development Boards. The design demonstrates write and read operations of the configured IP. An internal PLL is used to drive the BRAM and BIST logic for write and read operations, ensuring the correctness of data from the BRAM. BIST writes to the BRAM and reads back from the BRAM to compare the writing. BIST sets 1 across data bits. BIST does a sequential write, followed by a read of 1 across all data bits and address bits.

You can observe the pass or fail status as indicated by the LED light, a locked PLL, or a test completion. Switches are used to reset and start the comparison.

The example design only supports a 1:1 ratio with width across a Single-port RAM, a Simple Dual-port RAM, and a True Dual-port RAM without an output pipe enabled. Neither the single-port ROM nor the dual-port ROM is supported in the example design.

Figure 1. BRAM Wrapper Example Design Block Diagram

Table 1. Inputs for Trion T120 F576 Development Board Design Example
Input Interface Signal Description
20 MHz Oscillator GPIOR_187 gpio_ref_clk Reference clock
SW6 GPIOB_RXP08 i_start_n USER_SWITCH0
SW7 GPIOB_RXN08 i_reset_n USER_SWITCH1
Table 2. LED Outputs for Trion T120 F576 Development Board Design Example
LED Interface Color Signal Description
D7 GPIOB_RXP04 Blue user_led0_blue USER_LED0. Test completed.
D8 GPIOB_RXN04 Green user_led0_green USER_LED1. Indicate PLL is locked but is not completed.
D9 GPIOB_RXP05 Red user_led0_red USER_LED2. Unused (set to low).
D12 GPIOB_RXN06 Blue user_led1_blue USER_LED5. Unused (set to low).
D13 GPIOB_RXP07 Green user_led1_green USER_LED6. Indicate a pass.
D14 GPIOB_RXN07 Red user_led1_red USER_LED7. Indicate a fail.
Table 3. Inputs for Titanium Ti60 F225 Development Board Design Example
Input Interface Signal Description
25 MHz Oscillator GPIOL_P18 gpio_pll_refclk PLL reference clock
SW1 GPIOR_29 i_start_n USER_BTN3
SW7 GPIOL_11 i_reset_n USER_BTN2
Table 4. LED Outputs for Titanium Ti60 F225 Development Board Design Example
LED Interface Color Signal Description
D16 GPIOR_P_07 Blue user_led0_blue USER_LED0. Test completed.
GPIOR_P_08 Green user_led0_green USER_LED0. Indicate PLL is locked but is not completed.
GPIOR_P_09 Red user_led0_red USER_LED0. Unused (set to low).
D17 GPIOR_N_07 Blue user_led1_blue USER_LED1. Unused (set to low).
GPIOR_N_08 Green user_led1_green USER_LED1. Indicate a pass.
GPIOR_B_09 Red user_led1_red USER_LED1. Indicate a fail.
Table 5. Trion T120 F576 Design Example Implementation
Inputs Outputs Clocks Logic Elements Memory Blocks Multipliers Worst Negative Slack (WNS) (ns) Worst Hold Slack (WHS) (ns) pll_inst1_
CLKOUT (MHz)
 fMAX (MHz) Efinity Version
4/1,546 (0.3%) 7/2,498 (0.3%) 1/16 (6.3%) 85/ 112,128 (0.08%) 1/1,056
(0.09%)
 0/320
(0%)
 3.14 0.086 145.77 140 2026.1
Table 6. Titanium Ti60 F225 Design Example Implementation
Inputs Outputs Clocks XLRs Memory Blocks DSP Blocks Worst Negative Slack (WNS) (ns) Worst Hold Slack (WHS) (ns) pll_inst1_
CLKOUT (MHz)
 fMAX (MHz) Efinity Version
4/1,703 (0.2%) 7/2,267 (0.3%) 1/64 (1.6%) 85/ 60,800 (0.1%) 1/ 256
(0.4%)
 0/160
(0%)
 0.094 0.026 524.66 500 2026.1