BRAM Wrapper Example Design

You can choose to generate the example design when generating the core in the IP Manager Configuration window. Compile the example design project and download the .hex or .bit file to your board. To generate example design, the Example Design Deliverables Option signal must be enabled.

The example design targets the Titanium Ti60 F225 and Trion T120 F576 Development Boards. The design demonstrates write and read operations with the default settings. The system reset is tied to logic low so that the example design runs from start of write state to the end of read state and enters the idle state. The test pattern block produces 16-bit data width which is directly written into the Simple Dual-port RAM (configured as 1:1 ratio and synchronous clock setting).

Then, the read data from the test pattern block are compared with the read data from Simple Dual-port RAM on every clock cycle. You can observe the LED light indicator to observe the pass or fail status.