Optional Pipeline Register

The APB Interconnect core allows user to optimize latency and/or performance with the optional pipeline registers.

  • Input Register—Enable this register to optimize timing but adds one clock latency at the master interface input paths that includes s_apb_psel_i, s_apb_penable_i, s_apb_pwrite_i, s_apb_paddr_i, s_apb_pwdata_i, s_apb_pwdata_par_i, s_apb_pstrb_i, and s_apb_pstrb_par_i.
  • Output Register—Enable this register to optimize timing but adds one clock latency at the master interface output paths that includes s_apb_pready_o, s_apb_pslverr_o, s_apb_prdata_o, and s_apb_prdata_par_o.
  • Optimize Latency—Enable this parameter to optimize latency at the slave interface that includes apb_sel_o, apb_penable_o, apb_pwrite_o, apb_paddr_o, apb_pwdata_o, apb_pwdata_par_o, apb_pstrb_o, and apb_pstrb_par_o.
Note: When both the input and output register are enabled, there are an additional 2 latencies.

Figure 1. Read Operation Waveform with Input Register Enabled
Figure 2. Read Operation Waveform with Output Register Enabled.
Figure 3. Read Operation Waveform with Input Register and Output Register Enabled
Figure 4. Write Operation Waveform with Optimize Latency Enabled