Functional Description

The APB Interconnect core is a bridge to arbitrate among multiple masters to a single slave based on priority level. The APB Interconnect core grants request to master with the selected priority. The APB Interconnect core thas two main interfaces:

• APB Master Interface—Provides 32 master interfaces to the APB Interconnect core.
• APB Slave Interface—Supports single slave interface.

The APB Interconnect core operates based on AMBA 3 APB protocol specifications. The following describes the general operation of the APB Interconnect core:

• When apb_eval is asserted, it indicates that APB Interconnect is in EVALUATION state, where it analyzes all masters' request and decide which master to grant.
• During EVALUATION state (i.e., apb_eval = 1), any assertion of PSEL marks the start of the APB request.
  • For an APB write request, PWRITE needs to assert too. PADDR and PWDATA contain destination address and the intended DATA to be written.
  • For an APB read request, PWRITE needs to be 0 while PADDR contains the address of the register to be read.
• The PENABLE signal needs to be 1 at one clock cycle after the assertion of PSEL for the APB request to be successful. The PENABLE assertion marks the start of transfer of the APB request.
• The PREADY signal is a return or response signal from the slave. The assertion PREADY indicates that the slave has completed the APB request.
• The PRDATA signal contains the result of the APB read request and it is valid when PREADY is 1.
• Masters' input signals (PSEL, PENABLE, PWRITE, PADDR, and PWDATA) need to be maintained throughout the APB request, i.e., from the assertion of PSEL until the assertion of PREADY.
• Upon receiving PREADY, master may change the PSEL, PENABLE, PWRITE, PADDR, and PWDATA signals for the next request or transfer.