APB Interconnect Core Example Design

You can access the example design from our portal on Ti375 PCIe® early access board. Compile the example design project and download the .hex or .bit file to your board.

Important: Efinix tested the example design generated with customized parameter options.

For this example design, the APB Interconnect core arbitrates among 3 masters to 1 APB interface (slave) to configure the PCIe Configuration Registers using the Titanium Ti375 N1156 Development Board. The example design contains a Virtual I/O debugger to issue read and write requests.

Furthermore, a logic analyzer is available to check for errors and compare the PRDATA with the PWDATA. The APB Interconnect core is set to Round-Robin mode, operates at 100 MHz, and enables Pipeline Registers at the masters' input paths (Register Input = Yes) and slave interface (Optimize Latency = No).

The APB Interconnect core configuration settings used in the example design are as follows:

Table 1. APB Interconnect Configuration Settings in Example Design
Parameter Value
Master Arbitration Mode Round-Robin
Number of Master 3
Address Width 24
Data Width 32
Register Input Yes
Register Output No
Optimize Latency No
Table 2. Titanium Ti375 N1156 Development Board Example Design Implementation
FPGA Logic Elements (Logic, Adders, Flipflops, etc.) Memory Blocks DSP Blocks fMAX (MHz)1 Efinity® Version
Ti375 N1156 C4 41,677/370,137 (11.25%) 290/2,688 (10.79%) 0/1344 (0%) 132.05 2024.1
1 Using parameter settings in Table 1.
2 Using System Verilog 2005.