Ports
| Port | Direction | Clock Domain | Description |
|---|---|---|---|
| clk | Input | – | Clock source for APB Interconnect core. |
| rst_n | Input | – | Active low asynchronous reset. |
| apb_eval | Output | clk | The assertion of this signal indicates that the APB Interconnect core is in EVALUATION
state. When this signal is asserted, APB Interconnect
core evaluates and decides which master to be granted a request. When
this signal is de-asserted, it means that APB Interconnect core has exited the EVALUATION state and is actively
granting a request to one of the masters. |
| grant_o[No. of Master-1:0] | Output | clk | This is a one-hot signal. The binary position of 1
in this signal indicates which master is being granted a request. For
example,
When grant_o is all-zeros, it means no master is being granted
a request. |
| Port | Direction | Clock Domain | Description |
|---|---|---|---|
| s_apb_psel_i[No. of Master-1:0] | Input | clk | APB select signal from the master, to request an APB transfer. |
| s_apb_penable_i[No. of Master-1:0] | Input | clk | APB enable signal from the master, to indicate the start of the APB request. |
| s_apb_pwrite_i[No. of Master-1:0] | Input | clk | APB write signal from the master, to indicate whether the APB request is a write or read request. |
| s_apb_paddr_i[No. of Master*Address Width-1:0] | Input | clk | APB address signal from the master, which contains the location of the destination register. |
| s_apb_pwdata_i[No. of Master*Data Width-1:0] | Input | clk | APB write data signal from the master, which contains the data
content to be written into the destination register. This signal is only
effective if APB write signal is 1. |
| s_apb_pwdata_par_i[No. of Master*(Data Width/8)-1:0] | Input | clk | APB write data parity signal from the master, which contains the data
parity of the APB write data. This signal is only effective if APB write
signal is 1. |
| s_apb_prdata_o[No. of Master*Data Width-1:0] | Output | clk | APB read data signal to the master, which contains data read from destination register (slave) as the result of APB read request. This signal is cycle accurate with APB ready signal. |
| s_apb_prdata_par_o[No. of Master*(Data Width/8)-1:0] | Output | clk | APB read data parity signal to the master, which contains data parity from the slave as the result of APB read request. This signal is cycle accurate with APB read data and APB ready signal. |
| s_apb_pready_o[No. of Master-1:0] | Output | clk | APB ready signal from the slave to the master. The assertion of this signal indicates that the active APB transfer has been completed. |
| s_apb_pslverr_o[No. of Master-1:0] | Output | clk | APB error signal from the slave to the master. The assertion of this signal indicates that an error has occurred during the APB transfer. |
| s_apb_pstrb_i[No. of Master*(Data Width/8)-1:0] | Input | clk | APB write strobe signal from the master. This signal enables the
write request with byte resolution. Each bit of this signal correlates
with a byte of APB write data. For example, when APB write strobe
is 4'b1001, both APB Write Data[31:24] and APB Write Data[7:0] are
intended to be written to the Destination Register[31:24] and
Destination Register[7:0], whereas APB Write Data[23:16] and APB
Write Data[15:8] are not intended to be processed, result in
Destination Register[23:16] and Destination Register[15:8] retaining
their original content. This signal is effective only
during write request. |
| s_apb_pstrb_par_i[Number of Master-1:0] | Input | clk | APB write strobe parity signal from the master, which is effective during write request only. |
| Port | Direction | Clock Domain | Description |
|---|---|---|---|
| apb_psel_o | Output | clk | APB select signal from the APB Interconnect core to the slave, to trigger an APB request. |
| apb_penable_o | Output | clk | APB enable signal from APB Interconnect core to
slave, to start an APB transfer at 1 clock cycle after APB
select. To comply with APB protocol, the APB Interconnect core evaluates the masters' APB enable
at 1 clock cycle after the assertion of masters' APB select, to
determine the start of the APB transfer. Refer to APB Interconnect Operations. |
| apb_pwrite_o | Output | clk | APB write signal from the APB Interconnect core to
the slave. When this signal is When this signal is 1, it refers to an
APB write request.0, it
refers to an APB read request. |
| apb_paddr_o[Address Width-1:0] | Output | clk | APB address from the APB Interconnect core to slave. Contains the address of the destination location. |
| apb_pwdata_o[Data Width-1:0] | Output | clk | APB write data signal from the APB Interconnect core to the slave, contains data content to be written into destination registers. This signal is effective only during a write request. |
| apb_pwdata_par_ o[(DataWidth/8)-1:0] |
Output | clk | APB write data parity signal from the APB Interconnect core to the slave, contains the data parity of the APB write data.
This signal is only effective if an APB write signal is
1. |
| apb_pstrb_o[(Data Width/8)-1:0] | Output | clk | APB write strobe signal from the APB Interconnect
core to the slave. This signal enables the write request with byte
resolution. Each bit of this signal correlates with a byte of the APB
write data. For example, when APB write strobe is 4'b1001, both APB
Write Data[31:24] and APB Write Data[7:0] are intended to be written
to the Destination Register[31:24] and Destination Register[7:0],
whereas APB Write Data[23:16] and APB Write Data[15:8] are not
intended to be processed, results in Destination Register[23:16] and
Destination Register[15:8] retaining their original
content. This signal is effective only during a write
request. |
| apb_pstrb_par_o | Output | clk | APB write strobe parity signal from the APB Interconnect core to the slave, which is effective only during a write request. |
| apb_prdata_i[Data Width-1:0] | Input | clk | APB read data signal from the slave to the APB Interconnect core which contains data read from the destination register (slave) as the result of an APB read request. This signal is cycle accurate with the APB ready signal. |
| apb_prdata_par_i[(Data Width/8)-1:0] | Input | clk | APB read data parity signal from the slave to the APB Interconnect core which contains data parity from the slave as a result of APB read request. This signal is cycle accurate with APB read data and APB ready signal. |
| apb_pready_i | Input | clk | APB ready signal from the slave to the APB Interconnect core. The assertion of this signal indicates that the active APB transfer has been completed. |
| apb_pslverr_i | Input | clk | APB error signal from the slave to the APB Interconnect core. The assertion of this signal indicates that an error has occurred during the APB transfer. |