Resource Utilization and Performance

Note: The resources and performance values provided are based on some of the supported FPGAs. These values are just guidance and may change depending on the device resource utilization, design congestion, and user design.
Table 1. Titanium Resource Utilization and Performance on PCIE Application
FPGA Arbitration Mode Resource fMAX (MHz)1 Efinity Version2
Logic Elements (Logic, Adders, Flipflops, etc.) Memory Block DSP Block
Ti375 N1156 C4 Fixed-Priority 1905/362,880 (0.52%) 0/2,688 (0%) 0/1,344 (0%) 210 2024.2
Round-Robin 2070/362,880 (0.57%) 0/2,688 (0%) 0/1,344 (0%) 194
Note:
  • The resource utilization is gathered from a design where the APB Interconnect core arbitrates 32 masters (the maximum number) with the quad 0 APB in Ti375 N1156 C4. The APB Interconnect core is configured with zero pipeline register to optimize latency.
  • You may choose to optimize fmax to meet your targeted performance by enabling any (or all) pipeline registers at Masters-APB Interconnect interface and APB Interconnect-slave interface.
Table 2. Titanium Resource Utilization and Performance on Soft IP Application
FPGA Arbitration Mode Resource fMAX (MHz)1 Efinity Version2
Logic Elements (Logic, Adders, Flipflops, etc.) Memory Block DSP Block
Ti375 N1156 C4 Fixed-Priority 896/362,880 (0.52%) 0/2,688 (0%) 0/1,344 (0%) 261 2024.2
Round-Robin 1633/362,880 (0.03%) 0/2,688 (0%) 0/1,344 (0%) 248
Note:
  • The resource utilization is gathered from a design where the APB Interconnect arbitrates 32 masters (the maximum number) with another soft IP as a slave in the design. Here, the APB Interconnect core is configured with zero pipeline register to optimize latency.
  • You may choose to optimize fmax to meet your targeted performance by enabling any (or all) pipeline registers at Masters-APB Interconnect interface and APB Interconnect-slave interface.
1 Using default parameter settings.
2 Using System Verilog 2005.