Signals

In the Efinity Interface Designer, signals are prefixed with a user-defined instance name. Efinix recommends using an instance name with the format Qn_Lm (where n is the quad number and m is the lane number) for easier identification.

Table 1. Signals per LaneWhere m is 0, 1, 2, or 3; x is a, b, c, d
Signal Direction Clock Domain Description
Clock and Reset
PCS_CLK_TX Input N/A (Hidden from user view)
TX PCS clock source.

Internally routed from TX_FWD_CLK and balanced with relevant clock networks.
PCS_CLK_RX Input N/A (Hidden from user view)
RX PCS clock source.

Internally routed from TX_FWD_CLK and balanced with relevant clock networks.
TX_FWD_CLK Output N/A
Forwarded MAC clock from the PCS. Source PCS_CLK_TX/RX from this clock.
In the Interface Designer, the TX_FWD_CLK signal is denoted by "Interface Clock Input Pin Name", indicating where the user needs to assign its name.

10M: 0.625 MHz
100M: 6.25 MHz
1G: 62.5 MHz
2.5G: 156.25 MHz
RX_FWD_CLK Output N/A Forwarded MAC clock from the PCS at 2× the MAC clock frequency.
This clock is used for clocking the 8-bit GMII MAC and 8-to-16-bit GMII adapter.
In the Interface Designer, the RX_FWD_CLK signal is denoted by "Interface Clock ×2 Input Pin Name", indicating where the user needs to assign its name.

10M: 1.25 MHz
100M: 12.5 MHz
1G: 125 MHz
2.5G: 312.5 MHz
Control
PMA_TX_ELEC_IDLE Input Async PMA TX electrical idle.
1: TX lines in an idle state.
0: Transmit data.
Error and Status
CTC_ERR Output PCS_CLK_RX CTC FIFO error occurred for each CTC module. This signal is clocked by the respective MAC clock for that lane/port. In 10G mode, this signal is rx_clk.
RX_ACTIVITY Output PCS_CLK_RX
Optional receive status activity LED output.
Exposed when the "Enable Activity Status for LED" option is ticked.
SYNC_STATUS Output PCS_CLK_RX Comma alignment synchronization status for lane n. If operating in GMII mode, each synchronization status is clocked by the respective MAC clock for that lane/port.
TX_ACTIVITY Output PCS_CLK_RX Optional transmit status activity LED output. Exposed when the "Enable Activity Status for LED" option is ticked.
Power Up
PMA_RX_SIGNAL_DETECT Output Async PMA receiver signal detect. Asserted high upon detection of the high-speed signal on RX differential inputs.
PMA_XCVR_PLLCLK_EN_ACK Output Async Link PLL clock enable acknowledgment. This signal indicates whether the pma_pllclk_datart_ln_m and pma_pllclk_-fullrt_ln_m for the associated link/port is running.
PMA_XCVR_PLLCLK_EN Input Async Link PLL clock enable. This signal cleanly gates the pma_pllck_datart_ln_m and pma_pllclk_fullrt_ln_m clocks for the associated link/port.
PMA_XCVR_POWER_STATE_​ACK[3:0] Output Async Link power state acknowledgment. This signal provides indication that a power state change request has completed.
4’b000000: Value after reset, prior to first power state request.
4’b0001: A0.
4’b0010: A1.
4’b0100: A2.
4’b1000: A3.
Once a power state is acknowledged, the value remains unchanged until a new power state is requested and the link has completed the transition to the new power state.
PMA_XCVR_POWER_STATE_​REQ[3:0] Input Async Link power state request. This signal changes the raw SerDes link/port’s power state. When the link/port has completed the transition to the requested power state, the requested state is reflected on PMA_XCVR_POWER_ STATE_ACK.
4’b0000: Idle.
4’b0001: A0 TX/RX active.
4’b0010: A1 Powerdown1 (low power state with minimum exit latency).
4’b000100: A2 Powerdown2 (lower power state with longer exit latency as compared to A1).
4’b1000: A3 Powerdown3 (lower power state and longer exit latency as compared to A2).
This is a one hot encoded signal. A subsequent change request shall not be signaled until the current request has been acknowledged and PMA_XCVR_POWER_STATE_REQ has returned to 0.
Upon reset release, the first power state must be A2.
SGMII
GMII_COL Output PCS_CLK_RX MII collision for port x. Supports half-duplex operation in 10/100M SGMII mode. Can be ignored in full duplex mode.
GMII_CRS Output PCS_CLK_RX MII carrier sense for port x. Supports half-duplex operation in 10/100M SGMII mode. Can be ignored in full duplex mode.
GMII_RX_DV[1:0] Output PCS_CLK_RX GMII receive data valid.
GMII_RX_ER[1:0] Output PCS_CLK_RX GMII receive error.
GMII_RXD[15:0] Output PCS_CLK_RX GMII receive data.
GMII_TX_EN[1:0] Input pcs_clk_tx GMII transmit enable.
GMII_TX_ER[1:0] Input PCS_CLK_RX GMII transmit error.
GMII_TXD[15:0] Input pcs_clk_tx GMII transmit data.
PCS_AN_COMPLETE Output apb_clk Optional status output when SGMII auto-negotiation is defined.
Single-cycle interrupt pulse to indicate completion of auto-negotiation for each port (x).
SGMII_MODE Input Async
2’b00: 10M SGMII mode
2’b01: 100M SGMII mode
2’b10: 1G mode
2'b11: 2.5G mode
When set to the 10/100M SGMII modes, the MAC clocks must be slowed down to 10/100th of the speed of the datapath clocks.
When set to 2.5G mode, the functionality is the same but the clock speed is more than doubled.
Table 2. Signals per Quad
Signal Direction Clock Domain Description
USER_APB_CLK Input N/A APB clock source, maximum 200 Mhz.
USER_APB_PADDR[23:0] Input user_apb_clk APB address.
USER_APB_PSEL Input user_apb_clk APB select.
USER_APB_PENABLE Input user_apb_clk APB enable.
USER_APB_PWRITE Input user_apb_clk APB write.
USER_APB_PWDATA[31:0] Input user_apb_clk APB write data.
USER_APB_PRDATA[31:0] Output user_apb_clk APB read data.
USER_APB_PREADY Output user_apb_clk APB ready.
PMA_CMN_READY Output Async PMA ready.
LED_TICK_TOGGLE Input Async A toggle signal used for timing LED activity signals for all lanes. This signal should toggle every 0.5 ms.
REM_PRE Input Async Optional 1G control signal. Remove one preamble byte if the number of idles is not even.