Power-Up Sequence
Initially, the SGMII reset controller controls the
phy_apb_reset_n and phy_cmn_reset_n signals.
phy_cmn_reset_n is handed over to the user application after the
assertion of pma_cmn_ready and the FPGA enters user mode. For the
power-up sequence to work correctly, the user application must drive the per-lane
phy_reset_n and phy_cmn_reset_n high in it's
initial state.
Upon the assertion of pma_cmn_ready,
pma_xcvr_power_state_req is set to 0x0 and
pma_xcvr_pllclk_en is asserted high. When
pma_xcvr_pllclk_en_ack goes high,
pma_xcvr_power_state_req is set to A2.
Note: There is a 100 ns (minimum) delay between the assertion of
pma_xcvr_pllclk_en_ack and the setting of
pma_xcvr_power_state_req to A2.