signal_ok Assertion Time

To help isolate the receive path during times when the clocking is unreliable, the PCS block implements a signal_ok signal such that it resets the whole receiver path, including returning the synchronisation state machine to the LOSS_OF_SYNC state, flushing the CTC buffers, and forcing the alignment state machine to LOSS_OF_ALIGN state. signal_ok should be deasserted whenever clocks are unreliable.

The client should program the signal_ok register bit high after RX calibration upon the assertion of the PMA signal, rx_signal_detect, so that the RX starts operation.

Figure 1. Asserting signal_ok

Table 1. signal__ok Timing Parameters
Timing Parameters Minimum Maximum Description
trx_cr_ceinit 2,001.613 μs 3,201.806 μs Initial time required to lock clock recovery once valid data is received.
trx_cr_noinit 1,389 ns 1,622 ns Time required to lock clock recovery once valid data is received, assuming initial adaptation has been previously completed.

To start RX operation, the client monitors the assertion of the PMA rx_signal_detect and waits for trx_cr_ceinit or trx_cr_noinit before programming signal_ok high.