Register Map

The following tables show the PCS registers.

Table 1. 1G PCS Register Access
1G PCS Access Value
USER_APB_PADDR[23:21] 3’b110
USER_APB_PADDR[20:11] x (Don’t care)
USER_APB_PADDR[10:8]
3’b100
Table 2. PCS Port Address Map
Port USER_APB_PADDR[7:0] Start USER_APB_PADDR[7:0] End
A 0x00 0x3C
B 0x40 0x7C
C 0x80 0xBC
D 0xC0 0xFC
Table 3. signal_ok Program Bit
Signal Address Write Bit
USER_APB_PADDR[23:0] 24’h600040
[14:11]
11: Lane 0
12: Lane 1
13: Lane 2
14: Lane 3
Table 4. Register Map
Register Type Reset Value Address Offset
PCS Control RW 0x00001040 0x00
PCS Status RO 0x00000109 0x04
AN Advertised Abilities RW 0x00000001 0x10
AN LP Abilities RO 0x00000000 0x14
SGMII CFG1 RW 0x000186A0 0x24
SGMII CFG2 RW 0x000186A0 0x28
Auto Negotiation Extended Status RO 0x00008000 0x3C

The following tables show the bit description for the PCS registers.

Table 5. PCS Control Register
Bit Name Description Type Reset
31:16 Reserved Reserved. RO 0
15 pcs_software_reset PCS software reset. Written by software to force the hardware logic into a reset state. This bit is self-clearing. When reading this bit, logic 1 is returned until the reset has. Writing logic 0 has no effect. This bit only resets the AN, TX, and RX GMII state machines.
RW
0
14 loopback_mode
Loopback mode. The ewrap output pin of the PCS reflects this control bit, and can be used to select loopback mode in the PHY transceiver.
0: Loopback mode disabled.
1: Loopback mode enabled
RW
0
13 speed_select_bit_1 Reserved set to 0. Used in conjunction with bit 6 to always indicate 1G operation. RO 0
12 enable_auto_neg Enable auto-negotiation. When set active high, auto-negotiation operation is enabled.
RW
1
11:10 reserved reserved RO 0
9 restart_auto_neg Restart auto-negotiation. When set active high, the hardware restarts auto-negotiation. This bit is self-clearing, but once set shall remain in this state until auto-negotiation has restarted. Writing logic 0 has no effect. RW 0
8
mac_duplex_state
Reserved set to 1. The PCS only supports full duplex operation. RO 1
7 reserved Reserved. RO 0
6 speed_select_bit_0 Reserved set to 1. Used in conjunction with bit 13 to always indicate 1G operation. RO 1
5:0 reserved Reserved. RO 0
Table 6. PCS Status Register
Bit Name Description Type Reset
31:16 reserved Reserved. RO 0
15 base_100_t4 Reserved. Set to 0, not supported. RO 0
14 base_100_x_full_duplex Reserved. Set to 0, not supported. RO 0
13 base_100_x_half_duplex Reserved. Set to 0, not supported. RO 0
12 mbps_10_full_duplex Reserved. Set to 0, not supported. RO 0
11 mbps_10_half_duplex Reserved. Set to 0, not supported. RO 0
10 base_100_t2_full_duplex Reserved. Set to 0, not supported. RO 0
9 base_100_t2_half_duplex Reserved. Set to 0, not supported. RO 0
8 extended_status Extended status. When set active high, indicates extended status information is present in the PCS auto-negotiation extended status register. This bit is hardwired to logic 1. RO 1
7:6 reserved Reserved. RO 0
5 auto_neg_complete Auto-negotiation complete. Set active high by the PCS hardware to indicate auto-negotiation has completed. RO 0
4 remote_fault Remote fault. Set active high if the link partner remote fault bits in the PCS auto-negotiation link partner ability register, indicates an error. Resets low when read. RO 0
3 auto_neg_ability
Auto-negotiation ability. This bit indicates whether the PCS has auto-negotiation ability and reflects the value of the auto-negotiation enable bit in the PCS control register.
0: PCS is not able to perform auto-negotiation.
1: PCS is able to perform auto-negotiation
RO 1
2 link_status Link status. Indicates the status of the physical connection to the link partner. When set to logic 1 the link is up, and when set to logic 0, the link is down. If auto-negotiation is disabled this returns the synchronisation status. Held at logic 0 if the link goes down until this bit is read. RO 0
1 reserved Reserved. RO 0
0 extended_capabilities Extended register capabilities. When set active high, indicates the PCS supports extended register capabilities. This bit is hardwired to logic 1. RO 1
Table 7. Auto-Negotiation Advertised Abilities Register
Bits Name Description Type Reset
31:16 reserved Reserved RO 0
15 link 1 = Link up
0 = Link down
 RW 0
14:13 reserved Reserved RO 0
12 duplex_mode 1 = Full duplex
0 = Reserved
 RW 0
11:10 speed 11 = Reserved
10 = 1,000 Mbps
01 = 100 Mbps
00 = 10 Mbps
 RW 0
9:1 reserved Reserved RO 0
0 sgmii_mode Reserved RW 1
Table 8. Auto-Negotiation Link Partner Abilities
Bit Name Description Type Reset
31:16 reserved Reserved. RO 0
15 link_partner
Link status.
0 : Link down.
1 : Link up.
RO 0
14 link_partner_acknowledge Link partner acknowledge. Indicates that the link partner has successfully received the transmitted base page RO 0
13:12 link_partner_remote_fault_​duplex_mode
Bit 13: Reserved. Read as zero.
Bit 12 : Duplex mode.
RO 0
11:9 speed
11: Reserved
10: 1,000 Mbps
01: 100 Mbps
00: 10 Mbps
Bit 9: Reserved. Read as zero.
 RO 0
8:5 reserved
Reserved. Read as zero.
RO 0
4:0 reserved Reserved. RO 0
Table 9. SGMII CFG1
Bit Name Description Type Reset
31:27 reserved Reserved. RO 0
26 uni_direct_en When set, the auto-negotiation state machine allows the transmit state machine to transmit data when the link is down instead of idle ordered sets.
RW
0
25 alt_sgmii_an_mode Alternate SGMII mode. When set, along with bit 24, during auto-negotiation configuration data exchange a fixed value of 0x4001 is used for the configuration data.
RW
0
24 sgmii_an_mode SGMII AN mode. Set to configure auto-negotiation in accordance to SGMII specification.
RW
0
23:21 reserved Reserved. RO 0
20:0 an_link_timeout_val Auto-negotiation link timer timeout value in xcv_rbc clock cycles. This bit should be set to the equivalent 1.6 ms in SGMII mode and 10 ms in other modes.
RW
0x0186A0
Table 10. SGMII CFG2
Bit Name Description Type Reset
31:21 reserved Reserved. RO 0
20:0 an_link_fail_timeout_val Auto-negotiation link fail timer timeout value in xcv_rbc clock cycles. This bit should be set to the equivalent of 10 ms.
RW
0x0186A0
Table 11. Auto-Negotiation Extended Status
Bit Name Description Type Reset
31:16 reserved Reserved. RO 0
15 full_duplex_1000base_x Full duplex 1000BASE-X. Hardwired to logic 1, indicates the PCS can support full duplex operation of 1000BASE-X. RO 1
14 half_duplex_1000base_x Half duplex 1000BASE-X. Hardwired to logic 0, indicates the PCS cannot support half duplex operation of 1000BASE-X. RO 0
13 full_duplex_1000base_t Full duplex 1000BASE-T. Hardwired to logic 0, indicates the PCS cannot support 1000BASE-T full duplex operation. RO 0
12 half_duplex_1000base_t Half duplex 1000BASE-T. Hardwired to logic 0, indicates the PCS cannot support 1000BASE-T half duplex operation. RO 0
11:0 reserved Reserved. RO 0
Table 12. 1G PCS Lane Configuration
Bit Name Description Type Reset
31:19 reserved Reserved. RO 0
18:15 cfg_sgmii_clkdiv_en_p0
cfg_sgmii_clkdiv_en_p1
cfg_sgmii_clkdiv_en_p2
cfg_sgmii_clkdiv_en_p3
Auto-negotiation clock rate change enable:
18: Lane 3
17: Lane 2
16: Lane 1
15: Lane 0
RW 11
14:11 signal_ok
PCS signal_ok program bit. To start the PCS RX operation:
14: Lane 3
13: Lane 2
12: Lane 1
11: Lane 0
RW 0
10:9 test_sel
Selects the test pattern to be transmitted:
00: High-frequency Test Pattern (0101010101010101..)
01: Low-frequency Test Pattern (11111000001111100..)
10: Mixed-frequency Test Pattern (111110101100000..)
11: Reserved
RW 0
8 test_enable Enables the transmission of the selected test pattern. RW 0
7:4 polarity_inv_tx
Invert 20-bit polarity on transmit:
7: Lane3
6: Lane2
5: Lane1
4: Lane0
RW 0
3:0 polarity_inv_rx
Invert 20-bit polarity on receive:
3: Lane3
2: Lane2
1: Lane1
0: Lane0
RW 0
To program the special PCS lanes configuration in Table 12, use the following APB address:
  • USER_APB_PADDR[23:0]—24’h600040
1 Change to 1 in HWTCL.