Clock Sources

The MAC controller clock is derived directly from the PMA PLL; however, the clock frequency is configuration dependent.

Table 1. Clock Sources
Clock	Direction	Frequency (MHz)	Descriptions
TX_FWD_CLK (Interface_Clock_Pin)	Output	0.625–156.25	Forwarded MAC clock from the PCS.
USER_APB_CLK	Input	20–200	APB interface clock

In the Efinity Interface Designer the PCIe block has an option Reference clock from on-board crystal. If you turn this option off, you need to create a PLL instance with a specific PLL resource and settings as the temporary PCIe reference clock while the PHY is configuring. When the PHY completes configuration, the reference clock reverts to the edge card connector.

If you turn this option off, use these settings:

Create a PLL block with a resource of BR0 or BR1.
Enable the CLKOUT4 signal for the PLL. This signal is the temporary PCIe reference clock.
Use GPIOR_140 (BR0) or GPIOR_141 (BR1) as the PLL reference clock resource.
Configure the PLL in local feedback mode.

You can use the CLKOUT4 signal as a clock source for core logic after the PHY completes configuration.

Important: Turning off the reference clock from the on-board crystal is applicable to the Q0 and Q2 only. Efinix recommends you to provide a free running clock to Q1 and Q3 for proper configuration.

Important: Refclk0 is required for a transceiver quad to run the SGMII interface. At least one instance within the quad must connect to refclk0 in your board design.