Recommended Design Practice

Instantiate the High-Performance Sapphire RV32 SoC and Soft Logic Block Using the IP Manager

Before you integrate your design with the High-Performance Sapphire RV32 SoC, you need to generate the RISC-V block and soft logic block together, with the PLL and GPIO resource allocation, and pin assignment. This first step allows you to bring up a working design and having a reference for your next-step debugging. You are free to change the configuration, pins, or block resources later with the interface designer as you can bypass the interface designer configuration update shall you require to re-generate the soft logic block design files with the custom interface designer configuration.

PLL Utilization

The High-Performance Sapphire RV32 SoC requires at least 3 crucial clocks:
  • System clock—Drives most of the logic within the SoC including CPUs, FPU, MMU, caches, on-chip RAM, etc.
  • Memory clock—Drives the AXI path to communicate with the DDR controller.
  • DDR controller clock—Input clock for the DDR controller.
Note: Efinix recommends you use the same PLL to drive the clocks to save the utilization of PLL. Only three PLLs are supported to deliver the clock path to RISC-V block. If you have doubts about the PLL assignment, you may generate the working design with IP Manager.
The following table shows the assignment of the clock.
Table 1. Clock Assignment
PLL Resource Output Clock Functionality
PLL_BL0 and PLL_BL2 Clock 1 System clock
Clock 2 Memory clock
Clock 3 DDR clock
PLL_BL1 Clock 1 Memory clock
Clock 2 System clock
Clock 3 DDR clock

Soft Logic Block Design Files

The IP Manager generates the design files for soft logic block when you generate the High-Performance Sapphire RV32 SoC block. You can see the output files, EfxSapphireHpSoc_slb.v and EfxSapphireHpSoc_wrapper.v.

The EfxSapphireHpSoc_slb.v is the design file that does the following:
  • Handles master reset control
  • LPDDR4 controller reset and calibration control
  • Connects with the selected peripherals in the IP Manager
  • Establish a connection between peripherals and user interrupt ports
  • Establish a connection between the SoC debug module and the FPGA user tap or GPIO
Table 2. I/O Configuration Signal
Pin Direction Description
io_gpio_sw_n Input Active low master reset. It resets the high-performance SoC block and soft logic block (SLB) when active. It is usually connected to the external GPIO. However, it can connect to other sources as well.
io_asyncReset Output Active high reset signal for the high-performance SoC block.
pll_peripheral_locked Input PLL lock signal for peripherals. Connect to logic high if unused.
pll_system_locked Input PLL lock signal for high-performance SoC block. Connect to logic high if unused.
cfg_start Output DDR4 controller calibration start signal.
cfg_sel Output DDR4 controller calibration select signal.
cfg_reset Output DDR4 controller reset signal.
cfg_done Output DDR4 calibration done signal.

The EfxSapphireHpSoc_wrapper.v is the example top file for you to refer to and is optional to be included in the project for compilation. You can open and copy the EfxSapphireHpSoc_wrapper.v file to your own top file in directory ip/EfxSapphireHpSoc_slb/. Including the wrapper file in the project compilation list is not recommended. The file can revert to the default design whenever you regenerate the block using IP Manager.

Handling SoC Interfaces

The High-Performance Sapphire RV32 SoC provides the following:
  • Custom instruction interface
  • AXI master and slave interface
  • 24 user interrupt ports to interact with soft logic from FPGA core fabric
You can use a custom instruction interface to deliver the custom ALU for CPU, an AXI slave interface for direct memory access, an AXI master for peripheral communication, and interrupt ports for triggering to access priority routine. However, this can block the SoC from out of reset state if you enable the interfaces but left them unconnected in a design. Hence, you must connect the pins below to a known state even if your design is not ready in the first place.
No further action is required if you disable the interface in the IP Manager.
Table 3. Clock Assignment
Interface Pin State
Custom Instruction cpuX_customInstruction_cmd_ready High
AXI Slave io_ddrMasters_0_b_ready High
io_ddrMasters_0_r_ready High