Comparison with Sapphire RV32 SoC

While the High-Performance Sapphire RV32 SoC architecture shares similarities with the High-Performance Sapphire RV32 SoC, there are notable differences to consider:

Sapphire RV32 SoC
  • User peripherals connected via internal bus.
  • No data coherency between CPU and DMA via AXI Slave port.
  • Absence of a branch predictor.
  • Uses a shared FPU configuration for multi-core setups.
  • Supports up to 4 configurable hardware breakpoints.
High-Performance Sapphire RV32 SoC
  • User peripherals are segmented into separate modules, with EfxSapphireHpSoc_slb connected via AXI master interface. Note that the base address and AXI master interface are dedicated to this module. If additional modules require AXI mastere access, an AXI interconnect IP can facilitate connections to both EfxSapphireHpSoc_slb and your module.
  • Ensure data coherency between CPU and DMA via AXI Slave port, potentially eliminating the need for data cache flushing.
  • Features an integrated static branch predictor.
  • Dedicated FPU per core.
  • Supports 8 hardware breakpoints for debug module.