System & Core Features

System & Core Feature demos for the Efinix Sapphire SoC.

These demos cover multi-core SMP processing, output via semihosting, custom RISC-V instructions, floating-point acceleration, and L2 cache management.

The following guides provide step-by-step instructions for setting up and executing each demo:

Available Demos
🥾	Bootloader	Demonstrates the bootloader initialization sequence and memory setup on Sapphire SoC.
🔀	SMP Demo	Symmetric Multi-Processing demo showing task distribution across multiple RISC-V cores.
🖥️	Semihosting Demo	Demonstrates printf output via OpenOCD semihosting through the JTAG debug probe.
⏱️	SMP Timer Interrupt Demo	Shows per-core timer interrupt handling in a multi-core SMP environment.
🔢	Floating-Point Unit (FPU) Demo	Perform various mathematical operations such as calculating sine, cosine, tangent, square root, and division with time sampling.
🛠️	Custom Instruction Demo	Demonstrates how to invoke custom RISC-V instructions added to the Sapphire SoC pipeline.
💾	L2 Cache Flushing Demo	Shows how to flush the L2 cache via the AXI-B interface for cache coherency management.

Bootloader SMP Demo Semihosting Demo SMP Timer Interrupt Demo Floating Point Unit Demo Custom Instruction Demo L2 Cache Flusing Demo (axiBDemo)