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SMP Timer Interrupt Demo

This demo (smpTimerIntrDemo directory) demonstrates how different hardware cores can independently handle separate timer interrupts.

Both cores will print a message to the terminal when their respective timers trigger. However, Core 0 is configured to trigger and print twice as often as Core 1.

Newlib

By default, newlib-nano is used for this demo.

See also
User Debug Configuration - To learn more about User Debug Configuration.

Execution Sequence:

The following shows the expected execution sequence:

Starting SMP User Timer Interrupt Demo
Timer 0 ISR .. from hart 0
Timer 0 ISR .. from hart 0
Timer 1 ISR .. from hart 1
Timer 0 ISR .. from hart 0
Timer 0 ISR .. from hart 0
Timer 1 ISR .. from hart 1
Timer 0 ISR .. from hart 0
Timer 0 ISR .. from hart 0
Timer 1 ISR .. from hart 1
Timer 0 ISR .. from hart 0
Timer 0 ISR .. from hart 0
Timer 1 ISR .. from hart 1
Timer 0 ISR .. from hart 0
Timer 0 ISR .. from hart 0
Timer 1 ISR .. from hart 1