Resource Utilization and Performance

Note: The resources and performance values provided are based on some of the supported FPGAs. These values are just guidance and may change depending on the device resource utilization, design congestion, and user design.

Table 2. Titanium Resource Utilization and PerformanceMIPI DSI TX Controller with 4 data lanes.
FPGA	Logic Elements (Logic, Adders, Flipflops,etc.)	Memory Blocks	DSP Blocks	f_MAX (MHz)¹				Efinity® Version²
FPGA	Logic Elements (Logic, Adders, Flipflops,etc.)	Memory Blocks	DSP Blocks	clk	axi_clk	clk_byte_HS	clk_pixel	Efinity® Version²
Ti60 F225 C4	5,737 / 60,800 (9.44%)	35/256 (13.67%)	0/160 (0%)	205	252	227	261	2023.2.307.4.14

¹ Using default parameter settings.

² Using System Verilog.