Functional Description

The MIPI DSI TX Controller core consists of a TX D-PHY block, control status registers, ECC generator, CRC generator, packetizer, pixel-to-byte converter, and video interface detector. The core has a video, AXI4-lite, MIPI TX I/O, and clock and reset interfaces.

The MIPI DSI TX Controller core consists of a control status registers, ECC generator, CRC generator, packetizer, pixel-to-byte converter, and video interface detector. The core has a video interface which is running at pixel clock domain, AXI4-lite interface, clock and reset interface, and PPI interface which is running at MIPI byte clock domain. The DSI TX controller communicates with the MIPI hard D-PHY in the core device through the PPI interface.

Figure 1. MIPI DSI TX Controller System Block Diagram

Figure 2. MIPI DSI TX Controller System Block Diagram