Register Definition

Table 1. Control Status Registers
Word Offset Bits Name R/W Width (bits)
0x00 4:0 Interrupt status register. R/W1C 5
0x04 4:0 Interrupt enable register. R/W 5
0x08 7:0 PHY stop state status. RO 8
0x0C 0 TxUlpsActiveClkNot. RO 9
8:1 TxUlpsActiveNot_7: TxUlpsActiveNot_0.
0x10 7:0 Skew calibration high speed. R/W 8
0x14 0 UlpsClk. R/W 13
8:1 UlpsEsc[7:0].
12:9 TxTriggerEsc.
0x18 0 Reserved. R/W 4
1 Reserved.
2 Reserved.
3 video_stream_en.
1: Turn on HS video stream on the MIPI lane
0: Turn off HS video stream on the MIPI lane
0x1C HS Command Queue. Ensure that the bit 11 of the status register is low before issuing the next command. R/W 24
7:0 datatype.
15:8 Parameter 1.
23:16 Parameter 2.
0x20 LP Command Queue. Ensure that the bit 10 of the status register is low before issuing the next command. R/W 24
7:0 datatype.
15:8 Parameter 1.
23:16 Parameter 2.
0x24 19:0 Status register. RO 20
0x28 31:0 Low power command write long data FIFO.
You must write the LP write data to this FIFO before issuing the LP command packet to register 0x20.
Store only one complete write packet data in the FIFO at a time.
 WO 32
0x2C 31:0 High speed command write long data FIFO.
You must write the HS write data to this FIFO before issuing the HS command packet to register 0x1C.
Store only one complete write packet data in the FIFO.1
 WO 32
0x30 7:0 Low power command read long data FIFO.
The bus turnaround read data is pushed into this FIFO.
Store only one complete read packet data in the FIFO at a time. The MIPI DSI TX Controller stores all the return read data into the read FIFO and does not check whether the return read data matches maximum return packet size (MRPS).
 RO 8
0x34, 0x38, 0x3C Reserved
0x40 31:0 Total H line word count in byte. R/W 32
0x44 15:0 Horizontal sync active (HSA) in byte.
Only write to this register when it is sync pulse mode.
 R/W 16
0x48 15:0 Horizontal black porch (HBP) in byte.
For burst event mode, factor in HSA value into the HBP value.
 R/W 16
0x4C 15:0 Horizontal front porch (HFP) in byte. R/W 16
0x50 7:0 Vertical sync active (VSA) in line. The minimum number of lines is 1. R/W 8
0x54 7:0 Vertical black porch (VBP) in line. The minimum number of lines is 1. R/W 8
0x58 7:0 Vertical front porch (VFP) in line. The minimum number of lines is 2. R/W 8
0x5C 15:0 Vertical active (VACT) in line. The minimum number of lines is 1. R/W 16

Table 2. 0x24 Status Register Definition
Bit Description
0 lp_dcs_rfifo_full.
LP command read data FIFO full.
1 lp_dcs_rfifo_empty.
LP command read data FIFO empty.
2 lp_dcs_wfifo_full.
LP command write data FIFO full.
3 lp_dcs_wfifo_empty.
LP command write data FIFO empty.
4 hs_dcs_wfifo_full.
HS command write data FIFO full.
5 hs_dcs_wfifo_empty.
HS command write data FIFO empty.
6 Reserved.
7 Reserved.
8 Reserved.
9 Reserved.
10 lp_cmd_in_progress.
LP command transmission in LP lane is in progress.
Note: After writing LP cmd (addr: 0x20), lp_cmd_in_progress will not flag high immediately. Please wait at least 10 cycles of axi_clk prior to polling this indicator.
11 hs_cmd_in_progress.
HS command transmission in HS lane is in progress.
Note: After writing HS cmd (addr: 0x1c), hs_cmd_in_progress will not flag high immediately. Please wait at least 10 cycles of axi_clk prior to polling this indicator.
Table 3. 0x00 Interrupt Status Register Definition
Bit Description
0 Pixel FIFO full.
1 Pixel FIFO empty.
2 Unsupported video data type.
3 Turnaround timeout.
1 The word count for a HS write long command data has to be larger or equal than the number of MIPI data lane (NUM_DATA_LANE).