Customizing the MIPI DSI TX Controller
The core has parameters so you can customize its function. You set the parameters in the General tab of the core's IP Configuration window.
| Name | Option | Description |
|---|---|---|
| tLPX_NS | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. The tLPX_NS
ratio between host processor and peripheral must not exceed 3:2.
The host processor is responsible for controlling its own clock
frequency to match the peripheral. The host processor LP clock
frequency must be in the range of 67% to 150% of peripheral LP
clock frequency. Default: 50 |
| tINIT_NS | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. Default:
100000 |
| tLP_EXIT_NS | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. Default: 100 |
| Bus Turnaround Timeout Period | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. Default:
100000 |
| tD_TERM_EN_NS | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. This parameter dedicates to
the receiver timing from RX to TX during BTA function. Default:
35 |
| tHS_PREPARE_ZERO_NS | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns (value before adding UI).
This parameter describes the expected timing (combination
of tHS_PREPARE and tHS_ZERO) driven by
transmitter from RX to TX during BTA
function. Default: 145 |
| tCLK_ZERO_NS | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. Default: 262 |
| tCLK_TRAIL_NS | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. Default: 60 |
| tCLK_PRE_NS | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. Default: 10 |
| tCLK_POST_NS | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. Default: 60 |
| tCLK_PREPARE_NS | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. Default: 38 |
| tHS_PREPARE_NS | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns (value before adding
UI). Default: 40 |
| tWAKEUP_NS | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. Default:
1000 |
| tHS_EXIT_NS | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. Default: 100 |
| tHS_ZERO_NS | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns (value before adding
UI). Default: 105 |
| tHS_TRAIL_NS | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns (value before adding
UI). Default: 60 |
| NUM_DATA_LANE | 1, 2, 4 | Number of data lanes. Default: 4 |
| MIPI Parallel Clock Frequency | 10 – 187 | MIPI parallel clock frequency in MHz. Round down the frequency
value to an integer if there is any floating point from your
calculation. Default: 125 |
| IP Core Clock Frequency | 40 - 100 | IP core clock frequency in MHz. Default: 100 |
| DPHY_CLOCK_MODE | Continuous, Discontinuous
|
DHY clock mode. Default: Continuous |
| Pack Type 60 | Enable, Disable | Turn on pack 60-bit datatype. For example,
RGB101010. Default: Disable |
| Pack Type 48 | Enable, Disable | Turn on pack 48-bit datatype, for example, 20-bit YCbCr, 24-bit
YCbCr, 12-bit YCbCr, RGB666 (24-bit), or RGB888. Default:
Enable |
| Pack Type 64 | Enable, Disable | Turn on pack 64-bit datatype, for example, 16-bit YCbCr, or
RGB565. Default: Enable |
| Enable Bus Turnaround in vertical low power mode | Enable, Disable | Enables the bus turnaround during the last vertical front porch
line which goes into LP-11 state. Default:
Disable |
| Maximum Horizontal Resolution | Values according to video display | Maximum horizontal pixel resolution. Default:
1080 |
| Video Transmission Packet Sequences | Non-burst mode with Sync Pulses, Burst
mode, Non-burst mode with Sync Events |
Select video mode: 0: Non-Burst Mode with Sync
Pulses 1: Non-Burst Mode with Sync event
(default) 2: Burst Mode |
| High Speed Write Data FIFO DEPTH | 8 – 20481 | HS command write data FIFO depth. Default: 64 |
| Low power Write Data FIFO DEPTH | 8 – 20481 | LP command write data FIFO depth. Default: 64 |
| Low power Read Data FIFO DEPTH | 8 – 20481 | Bus turnaround read data depth. Default: 64 |
| Pixel Data FIFO Depth Size | 256 – 81921 | FIFO depth size to store the pixel packet data. (need to be set
to power of 2 value). Minimum FIFO depth required >
horizontal_pixel (HACT) x bits_per_pixel / 64 Default:
2048 |
| Enable End Of Transmission Packet | Enable, Disable | Enables or disables the End Of Transmission Packet. Default:
Disable |
| Enable bidirectional DPHY | Enable, Disable | To instantiate a unidirectional or bidirectional soft
D-PHY. Default: Enable |
| MIPI_DSI_TX_DEBUG | Enable, Disable | Enable debug ports for internal signal observation and
monitoring. Default: Disable |
1 2n, where n can
be from 3 to 11.