Ports

Table 1. Clock and Reset Ports
Port Direction Description
clk Input IP core clock consumed by controller logic. 100 MHz.
reset_n Input IP core reset signal.
clk_byte_HS Input MIPI TX parallel clock. This clock is a HS mode transmission clock.
reset_byte_HS_n Input MIPI TX parallel clock reset signal.
clk_pixel Input Pixel clock.
reset_pixel_n Input Pixel clock reset signal.
axi_clk Input AXI4-Lite interface clock.
axi_reset_n Input AXI4-Lite interface reset.
Table 2. MIPI TX I/O interface
Port Direction Description
Tx_LP_CLK_P Output LP mode TX clock single-ended P signal.
Tx_LP_CLK_P_OE Output Output enable for LP mode TX clock single-ended P signal.
Tx_LP_CLK_N Output LP mode TX clock single-ended N signal.
Tx_LP_CLK_N_OE Output Output enable for LP mode TX clock single-ended N signal.
Tx_HS_C [7:0] Output HS mode differential clock bus.
Tx_HS_enable_C Output Signal to enable HS mode clock lane.
Tx_LP_D_P [NUM_DATA_LANE-1:0] Output LP mode TX data single-ended P signal.
Tx_LP_D_P_OE [NUM_DATA_LANE-1:0] Output Output enable for LP mode TX data single-ended P signal.
Tx_LP_D_N [NUM_DATA_LANE-1:0] Output LP mode TX data single-ended N signal.
Tx_LP_D_N_OE [NUM_DATA_LANE-1:0] Output Output enable for LP mode TX data single-ended N signal.
Tx_HS_D_0[7:0] Output HS mode differential lane 0 data bus.
Tx_HS_D_1[7:0] Output HS mode differential lane 1 data bus.
Tx_HS_D_2[7:0] Output HS mode differential lane 2 data bus.
Tx_HS_D_3[7:0] Output HS mode differential lane 3 data bus.
Tx_HS_enable_D [NUM_DATA_LANE-1:0] Output Signal to enable HS mode data lane.
Rx_LP_D_P Input LP mode RX data single-ended P signal.
Rx_LP_D_N Input LP mode RX data single-ended N signal.
Table 3. Video InterfaceAll signals are clocked with clk_pixel and reset_pixel_n.
Port Direction Description
hsync Input Active-low horizontal sync.
vsync Input Active-low vertical sync.
datatype [5:0] Input Data type of the HS packet. Sampled at hsync rising edge.
pixel_data [63:0] Input Video Data. The actual width is dependent on pixel type. See Video Mode Pixel Encoding.
pixel_data_valid Input Active-high pixel data enable. Once the TX VALID signal goes high, the MIPI TX interface expects to receive pixel data every clock cycle until the entire line is sent. Additionally, the TX VALID signal must remain high for the entire line.
haddr [15:0] Input Number of horizontal pixels is 16-bit. Sampled at hsync rising edge.
vc [1:0] Input 2-bit virtual channel signal.
Table 4. Conduit Interface
Port Direction Description
TurnRequest_dbg Input User control turnaround request.
This active high signal indicates that the protocol needs to initiate a bi-directional data lane turnaround, allowing the other side to begin transmissions. TurnRequest is valid on the rising edge of clk. TurnRequest is only meaningful for a bidirectional data lane module that is currently the transmitter (Direction = 0). If the bi-directional data lane module is in receive mode (Direction = 1), this signal is ignored. A low-to-high transition on TurnRequest can only happen when Stopstate is asserted.
TurnRequest_done Output Indicates that the RX D-PHY acknowledges the bus turnaround or timeout. If this signal is high together with turnaround timeout, it indicates that there is no acknowledgement from the RX on the turnaround request.
irq Output Interrupt signal for interrupt status register.
Table 5. AXI4-Lite InterfaceAll signals are clocked with axi_clk.
Port Direction Description
axi_awaddr [6:0] Input AXI4-Lite write address bus.
axi_awvalid Input AXI4-Lite write address valid strobe.
axi_awready Output AXI4-Lite write address ready signal.
axi_wdata [31:0] Input AXI4-Lite write data.
axi_wvalid Input AXI4-Lite write data valid strobe.
axi_wready Output AXI4-Lite write ready signal.
axi_bvalid Output AXI4-Lite write response valid strobe.
axi_bready Input AXI4-Lite write response ready signal.
axi_araddr [6:0] Input AXI4-Lite read address bus.
axi_arvalid Input AXI4-Lite read address valid strobe.
axi_arready Output AXI4-Lite read address ready signal.
axi_rdata [31:0] Output AXI4-Lite read data.
axi_rvalid Output AXI4-Lite read data valid strobe.
axi_rready Input AXI4-Lite read data ready signal.

Table 6. Debug InterfaceAll signals are clocked with axi_clk and axi_reset_n.
Port Direction Description
mipi_debug_out[31:0] Output Debug port. Present if the parameter MIPI_DSI_TX_DEBUG is Enabled. The following is the list of internal signals that can be monitored.
[0] = fifo_full
[1] = fifo_empty
[2] = non_support_longpkt
[3] = turnaround_timeout
[4] = ready_to_xmit (indicator for initialization done, prior to skewcal)
[5] = init_skewcal_done (indicator for skewcal process completion)
[6] = lp_dcs_rfifo_full
[7] = lp_dcs_rfifo_empty
[8] = lp_dcs_wfifo_full
[9] = lp_dcs_wfifo_empty
[10] = hs_dcs_wfifo_full
[11] = hs_dcs_wfifo_empty
[12] = lp_cmd_in_progress
[13] = hs_cmd_in_progress
[14] = TxStopState_0
[15] = TxStopState_1
[16] = TxStopState_2
[17] = TxStopState_3
[18] = TxStopState_4
[19] = TxStopState_5
[20] = TxStopState_6
[21] = TxStopState_7
[31:22] = Reserved
mipi_debug_in[31:0] Input Debug ports. Present if the parameter MIPI_DSI_TX_DEBUG is Enabled.
Currently no function has been implemented. Tie all input bits to zero.
[31:0] = reserved