Ports

Table 1. Clock and Reset Ports
Port Direction Description
clk Input IP core clock consumed by controller logics. 100 MHz.
reset_n Input IP core reset signal.
clk_byte_HS Input MIPI RX parallel clock. This is a HS transmission clock.
reset_byte_HS_n Input MIPI RX parallel clock reset signal.
clk_pixel Input Pixel clock.
reset_pixel_n Input Pixel clock reset signal.
axi_clk Input AXI4-Lite interface clock.
axi_reset_n Input AXI4-Lite interface active low reset.
Note: Refer to the Interfaces User Guide in the Documentation page of the Support Center for serial or parallel clock requirements.
Table 2. PHY-Protocol Interface
Port Direction Description
RxUlpsClkNot Input Receive ULPS on Clock Lane. This bus is synchronized to axi_clk in the controller and stored in the CSR.
This active-low signal is asserted to indicate that the clock lane module has entered the ULPS due to the detection of a request to enter the ULPS.
RxUlpsActiveClkNot Input ULPS (not) Active. This bus is synchronized to axi_clk in the controller and stored in the CSR.
This active-low signal is asserted to indicate that the lane is in ULPS.
RxClkEsc [NUM_DATA_LANE-1:0] Input Escape mode Receive Clock. This escape clock is not used in the controller in the current core version. It is supplied by the MIPI hard D-PHY.
This signal is used to transfer received data to the protocol during escape mode.
RxErrEsc [NUM_DATA_LANE-1:0] Input Escape Entry Error. This bus is synchronized to axi_clk in the controller and stored in the CSR.
If an unrecognized escape entry command is received in LP mode, this active-high signal is asserted and remains asserted until the next transaction starts, so that the protocol can properly process the error.
RxErrControl [NUM_DATA_LANE-1:0] Input Control Error. This bus is synchronized to axi_clk in the controller and stored in the CSR.
This active-high signal is asserted when an incorrect line state sequence is detected in LP and ALP modes. Once asserted, this signal remains asserted until the next transaction starts, so that the protocol can properly process the error.
RxErrSotSyncHS [NUM_DATA_LANE-1:0] Input Start-of-Transmission Synchronization Error. This bus is be synchronized to axi_clk in the controller and stored in the CSR.
If the HS SoT leader sequence is corrupted in a way that proper synchronization cannot be expected, this active-high signal is asserted for one cycle of RxWordClkHS.
When ErrSotSyncHS is asserted, RxSyncHS, ErrSotHS, andRxValidHS is not asserted.
RxUlpsEsc [NUM_DATA_LANE-1:0] Input Escape ULPS. This bus is synchronized to axi_clk in the controller and stored in the CSR.
This active-high signal is asserted to indicate that the lane module has entered the ULPS, due to the detection of a received ULPS command.
RxUlpsActiveNot [NUM_DATA_LANE-1:0] Input ULPS (not) Active. This bus is synchronized to axi_clk in the controller and stored in the CSR.
This active-low signal is asserted to indicate that the lane is in ULPS.
RxSkewCalHS [NUM_DATA_LANE-1:0] Input HS Receive Skew Calibration. This bus is clocked by clk_byte_HS.
This optional active-high signal indicates that the high speed deskew burst is being received.
RxStopState [NUM_DATA_LANE-1:0] Input Data Lane in Stop State.
This asynchronous active-high signal indicates that the MIPI D-PHY data lane is currently in stop state.
RxSyncHS [NUM_DATA_LANE-1:0] Input Receiver Synchronization Observed. This bus is clocked by clk_byte_HS.
This active-high signal indicates that the Data lane has seen an appropriate synchronization event.
RxDataHSn [HS_DATA_WIDTH-1:0] Input HS data received by MIPI D-PHY data lane. This bus is clocked by clk_byte_HS.
n = lane 0 to 3
RxValidHSn [HS_DATA_WIDTH/8-1:0] Input This active-high signal indicates that the MIPI D-PHY data lane is driving data to the protocol layer on the RxDataHS output. This bus is clocked by clk_byte_HS.
RxValidHSn[0]: RxDataHS[7:0] contains valid data received from the channel
RxValidHSn[1]: RxDataHS[15:8] contains valid data received from the channel
n = lane 0 to 3

Table 3. AXI4-Lite Interface
Interface to access Table 1.
All signals are clocked with axi_clk and axi_reset_n.
Port Direction Description
axi_awaddr [15:0] Input AXI4-Lite write address bus.
axi_awvalid Input AXI4-Lite write address valid strobe.
axi_awready Output AXI4-Lite write address ready signal.
axi_wdata [31:0] Input AXI4-Lite write data.
axi_wvalid Input AXI4-Lite write data valid strobe.
axi_wready Output AXI4-Lite write ready signal.
axi_bvalid Output AXI4-Lite write response valid strobe.
axi_bready Input AXI4-Lite write response ready signal.
axi_araddr [15:0] Input AXI4-Lite read address bus.
axi_arvalid Input AXI4-Lite read address valid strobe.
axi_arready Output AXI4-Lite read address ready signal.
axi_rdata [31:0] Output AXI4-Lite read data.
axi_rvalid Output AXI4-Lite read data valid strobe.
axi_rready Input AXI4-Lite read data ready signal.
Table 4. Video InterfaceAll signals are clocked with clk_pixel and reset_pixel_n. The hsync_vc and vsync_vc are level signals and not pulse signals. See Video Timing Parameters.
Port Direction Description
hsync_vcx Output Active-high horizontal sync for virtual channel.
x = virtual lane 0 to 15
vsync_vcx Output Active-high vertical sync for virtual channel.
x = virtual lane 0 to 15
pixel_data [63:0] Output Video Data. The actual data width of this port is dependent on pixel type. Refer to the pixel encoding table.
pixel_data_valid Output Active-high pixel data enable.
pixel_per_clk [15:0] Output Number of pixel per pixel clock. This signal only valid when pixel_data_valid flag is high.

Table 5. Sideband InterfaceAll signals are clocked by clk_byte_HS except irq which is clocked by axi_clk.
Port Direction Description
vc [1:0] Output 2-bit virtual channel signal decoded from the packet header [7:6].
vcx [1:0] Output 2-bit virtual channel signal decoded from the packet header [25:24].
word_count [15:0] Output Byte count of the long packet received by CSI2 RX controller.
datatype [5:0] Output Decoded data type of incoming packet received by CSI2 RX controller.
shortpkt_data_field [15:0] Output 16-bit short packet data field for short packet.
irq Output Interrupt signal for Interrupt Status Register.
Table 6. Debug InterfaceAll signals are clocked with axi_clk and axi_reset_n.
Port Direction Description
mipi_debug_out[31:0] Output Debug port. Present if the parameter MIPI_CSI2_RX_DEBUG is Enabled. The following is the list of internal signals that can be monitored.
[0] = pixel_fifo_full
[1] = pixel_fifo_empty
[2] = crc_error
[3] = ecc_1bit_error
[4] = ecc_2bit_error
[5] = undersize_pkt_error
[6] = line_vc0_error
[7] = line_vc1_error
[8] = line_vc2_error
[9] = line_vc3_error
[10] = frame_vc0_error
[11] = frame_vc1_error
[12] = frame_vc2_error
[13] = frame_vc3_error
[14] = receive_error
[15] = init_done
[16] = RxErrSotSyncHS_0
[17] = RxErrControl_0
[18] = RxErrEsc_0
[19] = RxStopState_0
[20] = RxSkewCalHS_0
[21] = RxUlpsActiveNot_0
[22] = RxUlpsEsc_0
[31:23] = reserved
mipi_debug_in[31:0] Input Debug ports. Present if the parameter MIPI_CSI2_RX_DEBUG is Enabled.
Currently no function has been implemented. Tie all input bits to zero.
[31:0] = reserved
Table 7. Pixel Sideband InterfaceAll signals are clocked by clk_pixel and reset_pixel_n. These output ports are present when MIPI_CSI2_RX_PIXEL_SIDEBAND switch is set to ENABLE.
Port Direction Description
pixel_line_num[15:0] Output Line number decoded from the incoming short packet. This signal is valid or changes only when the hsync signal asserts from low to high.
pixel_frame_num[15:0] Output Frame number decoded from the incoming short packet. This signal is valid or changes when the vsync signal asserts from low to high.
pixel_datatype[5:0] Output Decoded data type of incoming packet received by the RX controller. This signal is valid or changes when the pixel_data_valid signal asserts from low to high.
pixel_wordcount[15:0] Output Decoded wordcount of incoming long packet received by the RX controller. This signal is valid or changes when the pixel_data_valid signal asserts from low to high.
pixel_vc[1:0] Output 2-bit virtual channel signal decoded from the packet header [7:6]. This signal is valid or changes when the vsync/hsync/pixel_data_valid signal asserts from low to high.
pixel_vcx[1:0] Output 2-bit virtual channel signal decoded from the packet header [25:24]. This signal is valid or changes when the vsync/hsync/pixel_data_valid signal asserts from low to high.