Pixel Clock Calculation

The following formula calculates the pixel clock frequency that you need to drive the pixel clock input port, clk_pixel.

PIX_CLK_MHZ >= (DATARATE_MBPS * NUM_DATA_LANE) / PACK_BIT,

where:
  • PIX_CLK_MHZ is the pixel clock in MHz
  • DATARATE_MBPS is the MIPI data rate in Mbps
  • NUM_DATA_LANE is the number of data lanes
  • PACK_BIT is the pixel data bits per pixel clock from Pixel Encoding

There is a FIFO for data transfer from the byte clock domain to the pixel clock domain. You are recommended to apply the pixel clock frequency approximately equal to the formula given. If the pixel clock frequency is too low, a FIFO overflow occurs (overflow happens when the read clock is slower than the write clock). If the pixel clock frequency is too high, a FIFO underflow occurs (which causes the pixel_data_valid to be in a toggling manner within a horizontal line). The maximum supported frequency for the pixel clock is 300 MHz.