Resource Utilization and Performance

Note: The resources and performance values provided are based on some of the supported FPGAs. These values are just guidance and may change depending on the device resource utilization, design congestion, and user design.

Table 1. Titanium Resource Utilization and PerformanceMIPI 2.5G CSI-2 RX Controller with 4 data lanes.
FPGA	Logic Elements (Logic, Adders, Flipflops, etc.)	Memory Blocks	DSP Blocks	f_MAX (MHz)¹				Efinity® Version²
FPGA	Logic Elements (Logic, Adders, Flipflops, etc.)	Memory Blocks	DSP Blocks	clk	axi_clk	clk_byte_HS	clk_pixel	Efinity® Version²
Ti180 J484 C4	3,658/17,280 (21%)	21/1,280 (1.6%)	0/640 (0%)	382	479	264	330	2024.2.294.2.12

¹ Using default parameter settings.

² Using Verilog HDL.