Functional Description

The MIPI 2.5G CSI-2 RX Controller consists of the following blocks:
  • Control Status Registers—Registers that the users can configure in runtime and statuses that user can read using the AXI4-lite interface
  • ECC Checker—Error correction code checker block
  • CRC Checker—Cyclic redundancy checker block
  • Depacketizer—Converts MIPI data to pixel data format
  • Lane Aligner—Aligns data lanes to each other
  • Lane FIFO—Manages clock domain conversion for the data from MIPI byte clock domain to pixel clock domain
  • Byte-to-Pixel Converter—Converts the 64-bit data from the packetizer to pixel data format and rearranges the data according to video data type
The core has a video, AXI4-lite, MIPI D-PHY, and clock and reset interfaces.
Figure 1. MIPI 2.5G CSI-2 RX Controller System Block Diagram