Customizing the MIPI 2.5G CSI-2 RX Controller
The core has parameters so you can customize its function. You set the parameters in the General tab of the core's IP Configuration window.
| Name | Options | Description |
|---|---|---|
| Data Lanes | 1, 2, 4 | Number of data lanes. Default: 4 |
| IP Core Clock Frequency | 40 - 100 | IP core clock frequency in MHz. Default: 100 |
| Pixel Data FIFO Depth Size | 256 - 8192 | FIFO depth size that stores the pixel packet data (set to power
of 2 value). Minimum FIFO depth required > horizontal_pixel
(HACT) x bits_per_pixel / 64 Default:
1024 |
| Image Frame Mode | Generic, Accurate | Selects image frame mode. Generic mode: Frame format without
accurate synchronization timing via Line Start and Line
End. Accurate mode: Frame format with accurate
synchronization timing via Line Start and Line
End. Default: Generic |
| Enable Extra Bit on Virtual Channel | Disable, Enable | Enables 16 virtual channel support. Default:
Disable |
| Enable Pipeline State for RXStopState Signal | 8 – 15 | Enable pipeline stage for RXStopState signal. The pipeline
registers are clocked with HS mode byte clock. Compensates the
MIPI HSIO deserializer, read FIFO and data synchronizer latency
in designs with low MIPI data rate. Default:
8 |
| Number of Asynchronous Register Stages | 2 – 8 | Cross clock domain control signal synchronization stage.
Default: 2 |
| tINIT_NS | Values according to MIPI D-PHY specifications. | PHY initialization period in ns. Value must be 400,000 or
more. Default: 400,000 |
| Pack Type 40 | Enable, Disable | Enables the controller to pack RAW10, RAW20, YUV_420_10, and
YUV_422_10 data type.1 Default: Enable |
| Pack Type 48 | Enable, Disable | Enables the controller to pack RAW6, RAW12, RAW24, RGB888, and
YUV_420_8_legacy data type.1 Default: Enable |
| Pack Type 56 | Enable, Disable | Enables the controller to pack RAW7 RAW14, and RAW28.1 Default: Enable |
| Pack Type 64 | Enable, Disable | Enables the controller to pack RAW8, RAW16, RGB444, RGB565,
RGB555, YUV_422_8, YUV_420_8, generic long packet, user define
8-bit, and embedded 8-bit non image packet.1 Default: Enable |
| PPI Interface Data Width | 16 | HS mode data width. Default: 16 |
| MIPI_CSI2_RX_DEBUG | Enable, Disable | Enables debug ports for internal signal observation and
monitoring. Default: Disable |
| MIPI_CSI2_RX_PIXEL_ SIDEBAND |
Enable, Disable | Enabels more sideband ports under pixel interface. Refer to
portlist for more details. Default: Disable |
1 Only enable the pack
type that you are using to save logic resources.