Tz50 PLL

Tz50 FPGAs have up to 4 PLLs to synthesize clock frequencies. The PLLs are located in the corners of the FPGA. You can use the PLL to compensate for clock skew/delay via external or internal feedback to meet timing requirements in advanced applications. The PLL reference clock has up to four sources. You can dynamically select the PLL reference clock with the CLKSEL port. (Hold the PLL in reset when dynamically selecting the reference clock source.)

The PLL consists of a pre-divider counter (N counter), a feedback multiplier counter (M counter), a post-divider counter (O counter), and output dividers (C).

At startup, Efinix recommends that you hold the PLL in reset until the PLL's reference clock source is stable.

Note: You can cascade PLLs. To avoid the PLL losing lock, Efinix recommends that you do not cascade more than two PLLs.
At startup, Efinix recommends resetting all cascaded PLLs. Hold the first PLL in reset until the PLL's reference clock source is stable. Hold the cascaded PLLs in reset until the previous PLL is locked.
Cascaded PLLs do not need a 50% duty cycle on the reference clock. However, the clock needs to meet the PLL minimum pulse width as specified in the data sheet.

Figure 1. PLL Block Diagram

The counter settings define the PLL output frequency:

Local and Core Feedback Mode Where:
FPFD = FIN / N
FVCO = (FPFD x M x O x CFBK ) 1
FPLL = FVCO / O
FOUT = (FIN x M x CFBK) / (N x C)
 FVCO is the voltage control oscillator frequency
FPLL is the post-divider PLL VCO frequency
FOUT is the output clock frequency
FIN is the reference clock frequency
FPFD is the phase frequency detector input frequency
O is the post-divider counter
C is the output divider
Note: Refer to the Tz50 PLL Timing and AC Characteristics for FVCO, FOUT. FIN, FPLL, and FPFD values.

Figure 2. PLL Interface Block Diagram
Table 1. PLL Signals (Interface to FPGA Fabric)
Signal Direction Description
CLKIN[3:0] Input Reference clocks driven by I/O pads or core clock tree.
CLKSEL[1:0] Input You can dynamically select the reference clock from one of the clock in pins.
RSTN Input Active-low PLL reset signal. When asserted, this signal resets the PLL; when de-asserted, it enables the PLL. De-assert only when the CLKIN signal is stable.
Connect this signal in your design to power-up or reset the PLL. Assert the RSTN pin for a minimum pulse of 10 ns to reset the PLL. Assert RSTN when dynamically changing the selected PLL reference clock.
FBK Input Connect to a clock out interface pin when the PLL is in core feedback mode.
IOFBK Input Connect to a clock out interface pin when the PLL is in external I/O feedback mode.
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
 Output PLL output. You can route these signals as input clocks to the core's GCLK network.
CLKOUT4 can only feed the top or bottom regional clocks.
All PLL outputs lock on the negative clock edge. The Interface Designer inverts the clock polarity on the leaf cells by default (Output Clock Inversion option unchecked). Check the option if you are using the clock to drive core logic.
You can use CLKOUT0 only for clocks with a maximum frequency of 4x (integer) of the reference clock. If all your system clocks do not fall within this range, you should dedicate one unused clock for CLKOUT0.
LOCKED Output Goes high when PLL achieves lock; goes low when a loss of lock is detected. Connect this signal in your design to monitor the lock status.
This signal is not synchronized to any clock and the minimum high or low pulse width of the lock signal may be smaller than the CLKOUT’s period.
SHIFT[2:0] Input (Optional) Dynamically change the phase shift of the output selected to the value set with this signal.
Possible values from 000 (no phase shift) to 111 (3.5 FPLL cycle delay). Each increment adds 0.5 cycle delay.
SHIFT_SEL[4:0] Input (Optional) Choose the output(s) affected by the dynamic phase shift.
SHIFT_ENA Input (Optional) When high, changes the phase shift of the selected PLL(s) to the new value.
Table 2. PLL Reference Clock Resource Assignments (F100)
PLL REFCLK0 REFCLK1 REFCLK2 External Feedback I/O
PLL_TL Single-ended: GPIOL_P_18_PLLIN0
Differential: GPIOL_P_18_PLLIN0, GPIOL_N_18
 Unbonded2 Unbonded2 Single-ended: GPIOL_P_17_EXTFB
Differential: GPIOL_P_17_EXTFB, GPIOL_N_17
PLL_TR Single-ended: GPIOR_P_19_PLLIN0
Differential: GPIOR_P_19_PLLIN0, GPIOR_N_19
 Unbonded2 Unbonded2 Unbonded2
PLL_BR Single-ended: GPIOR_P_00_PLLIN0
Differential: GPIOR_P_00_PLLIN0, GPIOR_N_00_CDI22
 Unbonded2 Unbonded2 Single-ended: GPIOR_P_01_EXTFB
Differential: GPIOR_P_01_EXTFB, GPIOR_N_01_CDI23
Table 3. PLL Reference Clock Resource Assignments (F225 and F256)
PLL REFCLK0 REFCLK1 REFCLK2 External Feedback I/O
PLL_BL Single-ended: GPIOL_P_00_PLLIN0
Differential: GPIOL_P_00_PLLIN0, GPIOL_N_00
 Single-ended: GPIOB_P_00_PLLIN1
Differential: GPIOB_P_00_PLLIN1, GPIOB_N_00
 Unbonded2 Single-ended: GPIOB_P_01_EXTFB
Differential: GPIOB_P_01_EXTFB, GPIOB_N_01
PLL_TL Single-ended: GPIOL_P_18_PLLIN0
Differential: GPIOL_P_18_PLLIN0, GPIOL_N_18
 Single-ended: GPIOT_P_00_PLLIN1
Differential: GPIOT_P_00_PLLIN1 GPIOT_N_00
 GPIOL_11_PLLIN2 Single-ended: GPIOL_P_17_EXTFB
Differential: GPIOL_P_17_EXTFB, GPIOL_N_17
PLL_TR Single-ended: GPIOR_P_19_PLLIN0
Differential: GPIOR_P_19_PLLIN0, GPIOR_N_19
 Single-ended: GPIOT_P_17_PLLIN1
Differential: GPIOT_P_17_PLLIN1, GPIOT_N_17
 Unbonded2 Single-ended: GPIOT_P_16_EXTFB
Differential: GPIOT_P_16_EXTFB, GPIOT_N_16
PLL_BR Single-ended: GPIOR_P_00_PLLIN0
Differential: GPIOR_P_00_PLLIN0, GPIOR_N_00_CDI22
 Single-ended: GPIOB_P_17_PLLIN1
Differential: GPIOB_P_17_PLLIN1, GPIOB_N_17
 GPIOR_29_PLLIN2 Single-ended: GPIOR_P_01_EXTFB
Differential: GPIOR_P_01_EXTFB, GPIOR_N_01_CDI23
1 (M x O x CFBK) must be ≤ 255.
2 There is no dedicated pin assigned to this reference clock.