Tz50 Features

  • High-density, low-power Quantum® compute fabric
  • Built on TSMC 16 nm process
  • 10-kbit high-speed, embedded SRAM, configurable as single-port RAM, simple dual-port RAM, true dual-port RAM, or ROM
  • High-performance DSP blocks for multiplication, addition, subtraction, accumulation, and up to 15-bit variable-right-shifting
  • Versatile on-chip clocking
    • Low-skew global network supporting 32 clock or control signals
    • Regional and local clock networks
    • PLL support
  • FPGA interface blocks
    • High-voltage I/O (HVIO) (1.8, 2.5, 3.3 V)
    • High-speed I/O (HSIO), configurable as:
      • LVDS, subLVDS, Mini-LVDS, and RSDS (RX, TX, and bidirectional), up to 1.3 Gbps
      • MIPI lane I/O (DSI and CSI) in high-speed (HS) low-power (LP) modes, up to 1.3 Gbps
      • Single-ended and differential I/O
    • PLL
    • Oscillator
  • Flexible device configuration
    • Standard SPI interface (active, passive, and daisy chain1)
    • JTAG interface
    • Supports internal reconfiguration
  • Single-event upset (SEU) detection feature
  • Fully supported by the Efinity® software, an RTL-to-bitstream compiler
  • Optional security feature
    • Asymmetric bitstream authentication using RSA-4096
    • Bitstream encryption/decryption using AES-GCM
Table 1. Tz50 FPGA Resources
Logic Elements (LEs) eXchangeable Logic and Routing (XLR) Cells Global Clock and Control Signals Embedded Memory (Mbits) Embedded Memory Blocks (10 Kbits) Embedded DSP Blocks
Total SRL82
52,160 55,786 12,380 Up to 32 2.4 235 140
Table 2. Tz50 Package-Dependent Resources
Resource F100 F225 F256
Single-ended GPIO (Max) HVIO (1.8, 2.5, 3.0, 3.3 V LVCMOS, 3.0, 3.3 V LVTTL) – 23 27
HSIO
LVCMOS, HSTL: 1.2, 1.5, 1.8 V
SSTL: 1.2, 1.35, 1.5, 1.8 V
 61 140 142
Differential GPIO (Max) HSIO (LVDS, Differential HSTL, SSTL, MIPI TX Data and Clock Lanes) 30 70 71
HSIO (MIPI RX Data Lanes) 21 58 59
HSIO (MIPI RX Clock Lanes) 3 12 12
Global clock or control signals from GPIO pins 8 15 16
PLLs 3 4 4
Notice: Refer to the Topaz Packaging User Guide for the package outlines and markings.
1 Daisy-chain is not supported in the F100 package.
2 Number of XLR that can be configured as shift register with 8 maximum taps.