Tz50 Configuration Timing
The Tz50 FPGA has the following configuration timing specifications.
Timing Parameters Applicable to All Modes
| Symbol | Parameter | Min | Typ | Max | Units |
|---|---|---|---|---|---|
| tCRESET_N | Minimum CRESET_N low pulse width required to trigger re-configuration. | 0.32 | – | – | μs |
| tUSER | Minimum configuration duration after CDONE goes high before entering
user mode. Test condition at 10 kΩ pull-up resistance and 10 pF
output loading on CDONE pin. |
25 | – | – | μs |
Note: The FPGA may go into user mode before
tUSER has elapsed. However, Efinix recommends that you keep the
system interface to the FPGA in reset
until tUSER has elapsed.
For JTAG programming, the min
tUSER configuration time is required after
CDONE
goes high and the FPGA receives the
ENTERUSER instruction from the JTAG host (TAP controller in UPDATE_IR
state).