Tz50 Revision History
| Date | Version | Description |
|---|---|---|
| February 2026 | 1.4 |
Updated DSP
block diagram; W register moved to after adder. (DOC-2592)
Corrected order of RBUF pins on the left and right in Tz50 Driving the Regional Network. (DOC-2783) Updated
Table 2.The Efinity software issues a warning (not
error) if you do not leave enough separation between GPIO and LVDS
or MIPI lane pins (see note). (DOC-2833) Added pull-down resistor
to HVIO figure Figure 1.
(DOC-2884) |
| October 2025 | 1.3 | Added notes for Tz50 Single-Event Upset Detection.
(DOC-2602) Updated Figure 4; some N signals were incorrectly labeled as P.
(DOC-2676) Updated Figure 1
due to incorrectly labeled buffers. Updated NSTATUS in
Table 2. |
| July 2025 | 1.2 | Added Tz50 HyperRAM Characteristics. (DOC-2520) Updated
configuration timing and fuse programming waveforms.
(DOC-2272) Moved table describing connection requirements
for unused resources and features to the Unused Resources and
Features topic. In Table 2, updated "When Configured As" column for Sub-LVDS and SLVS.
(DOC-2314) |
| November 2024 | 1.1 |
Added DLYCLK GPIO signal. (DOC-2159)
Updated GPIO and LVDS interface pin names (IN to I and OUT to
O) to align with primitives. (DOC-2086)
Removed PLL IOFBK interface pin.
The SAMPLE/PRELOAD instruction is available after JTAG fuses
have been blown. (DOC-2225)
Fixed typo in Table 2. (DOC-2038)
Changed column name from Pins to Configuration
Functions in Table 2. (DOC-2038)
Added note after Table 2 directing the reader to the pinout file.
(DOC-2038)
Updated Fuse Programming Requirements with details of VQPS current. (DOC-1999)
Added automotive grade to features. (DOC-1902)
Clarified which signals are
available when LVDS settings are enabled.
(DOC-1908)
Added reset recommendations for PLLs and
cascaded PLLs. (DOC-1900)
Clarified how to program the
SPI flash memory for F100S3F2 packages.
(DOC-1792)
Added notes to the configuration timing and security feature topics
about not using SPI and JTAG at the same time. (DOC-2047)
Updated configuration timing and fuse programming waveforns.
(DOC-2156)
Clarified HVIO and HSIO pin states during
configuration and when unused in user mode.
(DOC-2041) |
| October 2024 | 1.0 | Initial release. |